Secure memory repartitioning

Patent metadata

Field	Value
Publication number	US-9767044-B2
Application number	US-201314034813-A
Country	US
Kind code	B2
Filing date	Sep 24, 2013
Priority date	Sep 24, 2013
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Secure memory repartitioning technologies are described. A processor includes a processor core and a memory controller coupled between the processor core and main memory. The main memory includes a memory range including a section of convertible pages that are convertible to secure pages or non-secure pages. The processor core, in response to a page conversion instruction, is to determine from the instruction a convertible page in the memory range to be converted and convert the convertible page to be at least one of a secure page or a non-secure page. The memory range may also include a hardware reserved section that is convertible in response to a section conversion instruction.

First claim

What is claimed is:

1. A processor comprising:
a cache;
a processor core coupled to the cache; and
a memory controller coupled between the processor core and main memory, wherein the main memory comprises a memory range comprising a section of convertible pages that are convertible to secure pages or non-secure pages, wherein each of the convertible pages comprises a plurality of data lines, and wherein the processor core, in response to a page conversion instruction, is to:
determine from the page conversion instruction a convertible page in the memory range to be converted; and
convert the convertible page to be at least one of a secure page or a non-secure page, wherein the processor core, to convert the convertible page, is to:
change a bit in a page cache map corresponding to the convertible page, wherein the page cache map comprises an entry for each of the convertible pages in the section;
invalidate cached page contents for the convertible page stored in the cache; and
invalidate a translation mapping with an address of the convertible page.

2. The processor of claim 1 , wherein the page conversion instruction is a first conversion instruction, and wherein the processor core is to convert the convertible page from a non-secure page to a secure page in response to the first conversion instruction.

3. The processor of claim 2 , wherein the processor core is to perform the following in response to the first conversion instruction:
ensure that the address of the convertible page points to a page that is convertible to a secure page;
verify that the bit of the page cache map corresponding to the convertible page is set to be non-secure; and
set the bit of the page cache map to be secure.

4. The processor of claim 1 , wherein the page conversion instruction is a second conversion instruction, and wherein the processor core is to convert the convertible page from a secure page to a non-secure page in response to the second conversion instruction.

5. The processor of claim 4 , wherein the processor core is to perform the following in response to the second conversion instruction:
ensure that address of the convertible page points to a page that is convertible to a non-secure page;
verify that the bit of the page cache map corresponding to the convertible page is set to be secure;
verify that a valid bit of the page cache map is set to invalid; and
set the bit of the page cache map to be non-secure.

6. The processor of claim 1 , wherein the memory range further comprises a hardware reserved section, wherein the processor core, in response to a section conversion instruction, is to convert the hardware reserved section to be at least one of a secure section or a non-secure section.

7. The processor of claim 6 , wherein the section conversion instruction is a third conversion instruction, and wherein the processor core is to convert the hardware reserved section from a non-secure section to a secure section in response to the third conversion instruction.

8. The processor of claim 7 , further comprising a memory encryption engine (MEE) coupled between the processor core and the main memory, wherein the processor core is to perform the following in response to the third conversion instruction:
ensure that an address of the third conversion instruction points to a page in the hardware reserved section;
ensure that the hardware reserved section of the memory range is set as convertible, currently non-secure;
instruct the MEE to install a replay-protection filter for the hardware reserved section; and
instruct the MEE to put the hardware reserved section in an initialized state.

9. The processor of claim 6 , wherein the section conversion instruction is a fourth conversion instruction, and wherein the processor core is to convert the hardware reserved section from a secure section to a non-secure section in response to the fourth conversion instruction.

10. The processor of claim 9 , further comprising a memory encryption engine (MEE) coupled between the processor core and the main memory, wherein the processor core is to perform the following in response to the fourth conversion instruction:
ensure that an address of the fourth conversion instruction points to a page in the hardware reserved section;
ensure that the convertible pages in the section corresponding to the hardware reserved section are in a non-secure state;
instruct the MEE to uninstall a replay-protection filter for the hardware reserved section; and
instruct the MEE to flush contents of the hardware reserved section from its internal cache.

11. The processor of claim 6 , wherein the memory range further comprises another hardware reserved section that cannot be converted.

12. The processor of claim 11 , wherein the main memory comprises a non-secure memory range.

13. A method comprising:
decoding, by a processor core of a processor, a page conversion instruction to convert a convertible page in a memory range in main memory coupled to the processor core, wherein the memory range comprises a section of convertible pages that are convertible to secure pages or non-secure pages; and
executing, by the processor core, the page conversion instruction to convert the convertible page to be at least one of a secure page or a non-secure page wherein the executing further comprises:
changing a bit in a page cache map corresponding to the convertible page, wherein the page cache map comprises an entry for each of the convertible pages in the section;
invalidating cached page contents for the convertible page stored in a cache; and
invalidating a translation mapping with an address of the convertible page.

14. The method of claim 13 , further comprising:
converting, by the processor core, the convertible page from a non-secure page to a secure page when the page conversion instruction is a first conversion instruction; and
converting, by the processor core, the convertible page from the secure page to the non-secure page when the page conversion instruction is a second conversion instruction.

15. The method of claim 14 , further comprising:
in response to the first conversion instruction,
ensuring that the address of the convertible page points to a page that is convertible to a secure page;
verifying that the bit of the page cache map corresponding to the convertible page is set to be non-secure; and
setting the bit of the page cache map to be secure.

16. The method of claim 14 , further comprising:
in response to the second conversion instruction,
ensuring that the address of the convertible page points to a page that is convertible to a non-secure page;
verifying that the bit of the page cache map corresponding to the convertible page is set to be secure;
verifying that a valid bit of the page cache map is set to invalid; and
setting the bit of the page cache map to be non-secure.

17. The method of claim 14 , wherein the memory range further comprises a hardware reserved section, the method further comprises:
decoding, by the processor core, a section conversion instruction to convert the hardware reserved section in the memory range; and
executing the section conversion instruction to convert the hardware reserved section to be at least one of a secure section or a non-secure section.

18. The method of claim 17 , further comprising:
converting, by the processor core, the hardware reserved section from a non-secure section to a secure section when the section conversion instruction is a third conversion instruction; and
converting, by th

Assignees

• Intel Corp

Inventors

• Chhabra Siddhartha
• Savagaonkar Uday R
• Goldsmith Michael A
• Johnson Simon P
• Leslie-Hurd Rebekah M
• Mckeen Francis X
• Neiger Gilbert
• Makaram Raghunandan
• Rozas Carlos V
• Santoni Amy L
• Scarlata Vincent R
• Shanbhogue Vedvyas
• Smith Wesley H
• Anati Ittai
• Alexandrovich Ilya

Classifications

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F12/1408 Primary

  by using cryptography (for digital transmission H04L9/00) · CPC title

• G06F12/0808

  with cache invalidating means (G06F12/0815 takes precedence) · CPC title

• G06F2009/45587

  Isolation or security of virtual machine instances · CPC title

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title