Page state directory for managing unified virtual memory

Patent metadata

Field	Value
Publication number	US-9767036-B2
Application number	US-201314055318-A
Country	US
Kind code	B2
Filing date	Oct 16, 2013
Priority date	Mar 14, 2013
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

First claim

What is claimed is:

1. A system for managing virtual memory to physical memory mappings via a page state directory, the system comprising:
a first processing unit configured to execute a first operation that references a first virtual memory address;
a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault associated with the first virtual memory address upon determining that a first page table that is stored in a first memory associated with the first processing unit does not include a mapping corresponding to the first virtual memory address; and
a first copy engine associated with the first processing unit and configured to:
read one or more commands stored in a first command queue, and
in response, copy a first memory page from a second memory associated with a second processing unit to the first memory,
wherein the first processing unit and the second processing unit comprise different processor types,
wherein a first entry included in a page state directory includes a mapping of the first virtual memory address to a first physical memory address associated with the first memory page, and
wherein the page state directory includes virtual memory address-to-physical memory address mappings for memory pages stored in the first memory and virtual memory address-to-physical memory address mappings for memory pages stored in the second memory.

2. The system of claim 1 , wherein the page state directory has the first entry that includes the mapping, and wherein the page state directory further includes a first set of entries that includes the first entry and a second set of entries, the first page table including a first plurality of entries based on the first set of entries, and a second page table associated with the second processing unit and including a second plurality of entries based on the second set of entries.

3. The system of claim 2 , wherein each entry included in the first plurality of entries is based on a different entry included in the first set of entries, and each entry included in the second plurality of entries is based on a different entry included in the second set of entries.

4. The system of claim 2 , wherein the first entry further includes first state data that indicate that one of the first processing unit and the second processing unit has access to the first memory page that is associated with the mapping.

5. The system of claim 4 , wherein the first entry further includes second state data that indicate a first migration state associated with the first memory page.

6. The system of claim 2 , wherein the second processing unit is configured to execute a second operation that references the first virtual memory address.

7. The system of claim 6 , wherein:
the first entry is associated with the first processing unit,
the page state directory further includes a second entry that is associated with the first virtual memory address and the second processing unit, and wherein the second entry includes a second mapping that corresponds to the first virtual memory address, and
the first entry includes a forwarding entry that references the second mapping.

8. The system of claim 2 , further comprising a second page state directory, wherein the page state directory is associated with a first process, and the second page state directory is associated with a second process.

9. The system of claim 8 , wherein the first entry is associated with the first physical memory address, a second entry included in the second page state directory is also associated with the first physical memory address, and the second entry comprises a link to the first entry.

10. The system of claim 1 , wherein the page state directory comprises a multi-level table that includes leaf levels and non-leaf levels, leaf levels and non-leaf levels reflect different types of nodes in a tree structure, and a first non-leaf level included in the page state directory includes an array of pointers to a plurality of entries in a second level included in the page state directory.

11. A computing device for managing virtual memory to physical memory mappings via a page state directory, the computing device comprising:
a central processing unit;
a system memory associated with the central processing unit;
a first processing unit configured to execute a first operation that references a first virtual memory address, wherein the central processing unit and the first processing unit comprise heterogeneous processors;
a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault associated with the first virtual memory address upon determining that a first page table that is stored in a first memory associated with the first processing unit does not include a mapping corresponding to the first virtual memory address; and
a first copy engine associated with the first processing unit and configured to:
read one or more commands stored in a first command queue, and
in response, copy a first memory page from the system memory to the first memory,
wherein the central processing unit and the first processing unit comprise different processor types,
wherein a first entry included in a page state directory includes a mapping of the first virtual memory address to a first physical memory address associated with the first memory page, and
wherein the page state directory includes virtual memory address-to-physical memory address mappings for memory pages stored in the first memory and virtual memory address-to-physical memory address mappings for memory pages stored in the system memory.

12. The computing device of claim 11 , wherein the page state directory has the first entry that includes the mapping, and wherein the page state directory further includes a first set of entries that includes the first entry and a second set of entries, the first page table including a first plurality of entries based on the first set of entries, and a second page table associated with the central processing unit and including a second plurality of entries based on the second set of entries.

13. The computing device of claim 12 , wherein each entry included in the first plurality of entries is based on a different entry included in the first set of entries, and each entry included in the second plurality of entries is based on a different entry included in the second set of entries.

14. The computing device of claim 12 , wherein the first entry further includes first state data indicating that one of the central processing unit and the first processing unit has access to the first memory page that is associated with the mapping.

15. The computing device of claim 12 , wherein the central processing unit is configured to execute a second operation that references the first virtual memory address.

16. The computing device of claim 15 , wherein:
the first entry is associated with the first processing unit,
the page state directory further includes a second entry that is associated with the first virtual memory address and the central processing unit, and wherein the second entry includes a second mapping that corresponds to the first virtual memory address, and
the first entry includes a forwarding entry that references the second mapping.

17. A method for managing virtual memory to physical memory mappings via a page state directory, the method comprising:
executing a first operation that references a first virtual memory address;
generating a first page fault associated with the

Assignees

• Nvidia Corp

Inventors

• Duluk Jr Jerome F
• Buschardt Cameron
• Cheung Sherry
• Deming James Leroy
• Duncan Samuel H
• Dunning Lucien
• George Robert
• Gopalakrishnan Arvind
• Hairgrove Mark
• Jia Chenghuan
• Mashey John

Classifications

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F12/1072

  Decentralised address translation, e.g. in distributed shared memory systems · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/08

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title