Migrating pages of different sizes between heterogeneous processors

Patent metadata

Field	Value
Publication number	US-9424201-B2
Application number	US-201314134142-A
Country	US
Kind code	B2
Filing date	Dec 19, 2013
Priority date	Mar 14, 2013
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

One embodiment of the present invention sets forth a computer-implemented method for migrating a memory page from a first memory to a second memory. The method includes determining a first page size supported by the first memory. The method also includes determining a second page size supported by the second memory. The method further includes determining a use history of the memory page based on an entry in a page state directory associated with the memory page. The method also includes migrating the memory page between the first memory and the second memory based on the first page size, the second page size, and the use history.

First claim

What is claimed is:

1. A computer-implemented method for migrating a memory page from a first memory to a second memory, the method comprising:
determining a first page size supported by the first memory;
determining a second page size supported by the second memory;
determining a use history of the memory page based on an entry in a page state directory (PSD) associated with the memory page, wherein the use history includes a record of recent accesses of the memory page; and
migrating the memory page between the first memory and the second memory based on the first page size, the second page size, and the use history.

2. The method of claim 1 , wherein the first page size is smaller than the second page size, and migrating the memory page comprises transmitting the memory page from a system memory to a memory local to a parallel processing unit (PPU).

3. The method of claim 2 , further comprising transmitting at least one sibling memory page from the system memory to the memory local to the PPU, wherein the at least one sibling memory page is to be combined with the memory page to generate at least a portion of a larger memory page in the memory local to the PPU.

4. The method of claim 3 , further comprising coalescing an entry in a CPU page table corresponding to the memory page and an entry in the CPU page table corresponding to the at least one sibling memory page to generate an entry in a PPU page table corresponding to the larger memory page.

5. The method of claim 4 , wherein coalescing the entry in the CPU page table reduces the amount of space occupied by the memory page in the CPU page table corresponding to the memory page.

6. The method of claim 3 , further comprising combining the at least one sibling memory page with the memory page to generate the at least a portion of the large memory page based on an access frequency indicated by the use history of the at least one sibling memory page or the memory page.

7. The method of claim 1 , wherein the first size is larger than the second page size, and migrating the memory page comprises transmitting a first memory page from a memory local to a parallel processing unit (PPU) to a system memory.

8. The method of claim 7 , wherein migrating the memory page further comprises splitting the memory page in the PPU memory into a plurality of smaller memory pages that includes a second memory page, and transmitting the second memory page from the memory local to the PPU to the system memory.

9. The method of claim 8 , further comprising transmitting all of the other pages in the plurality of smaller memory pages from the memory local to the PPU to the system memory.

10. The method of claim 9 , further comprising removing an entry from a PPU page table corresponding to the memory page.

11. The method of claim 10 , wherein:
the use history indicates that both a CPU and a PPU have recently accessed data included in the first memory page, and, further comprising:
splitting the first memory page, and
transmitting the second memory page from the memory local to the PPU to the system memory.

12. The method of claim 1 , wherein the use history further includes a record of the number of recent accesses of the memory page.

13. A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause a computer system to migrate a memory page from a first memory to a second memory, by performing the steps of:
determining a first page size supported by the first memory;
determining a second page size supported by the second memory;
determining a use history of the memory page based on an entry in a page state directory (PSD) associated with the memory page, wherein the use history includes a record of recent accesses of the memory page; and
migrating the memory page between the first memory and the second memory based on the first page size, the second page size, and the use history.

14. The non-transitory computer-readable medium of claim 13 , wherein the first page size is smaller than the second page size, and migrating the memory page comprises transmitting the memory page from a system memory to a memory local to a parallel processing unit (PPU).

15. The non-transitory computer-readable medium of claim 14 , wherein the instructions further cause the computer system to transmit at least one sibling memory page from the system memory to the memory local to the PPU, wherein the at least one sibling memory page is to be combined with the memory page to generate at least a portion of a larger memory page in the memory local to the PPU.

16. The non-transitory computer-readable medium of claim 13 , wherein the first size is larger than the second page size, and migrating the memory page comprises transmitting a first memory page from a memory local to a parallel processing unit (PPU) to a system memory.

17. The non-transitory computer-readable medium of claim 16 , wherein migrating the memory page further comprises splitting the memory page in the PPU memory into a plurality of smaller memory pages that includes a second memory page, and transmitting the second memory page from the memory local to the PPU to the system memory.

18. A computing device for migrating a memory page, the computing device comprising:
a first memory;
a second memory;
a page state directory (PSD); and
a unified virtual memory (UVM) driver configured to:
determine a first page size supported by the first memory;
determine a second page size supported by the second memory;
determine a use history of the memory page based on an entry in the PSD associated with the memory page, wherein the use history includes a record of recent accesses of the memory page; and
migrate the memory page between the first memory and the second memory based on the first page size, the second page size, and the use history.

19. The computing device of claim 18 , wherein the first page size is smaller than the second page size, and migrating the memory page comprises transmitting the memory page from a system memory to a memory local to a parallel processing unit (PPU).

20. The computing device of claim 19 , wherein the UVM driver is further configured to transmit at least one sibling memory page from the system memory to the memory local to the PPU, wherein the at least one sibling memory page is to be combined with the memory page to generate at least a portion of a larger memory page in the memory local to the PPU.

21. The computing device of claim 18 , wherein the first size is larger than the second page size, and migrating the memory page comprises transmitting a first memory page from a memory local to a parallel processing unit (PPU) to a system memory.

22. The computing device of claim 21 , wherein migrating the memory page further comprises splitting the memory page in the PPU memory into a plurality of smaller memory pages that includes a second memory page, and transmitting the second memory page from the memory local to the PPU to the system memory.

Assignees

• Nvidia Corp

Inventors

• Duluk Jr Jerome F
• Buschardt Cameron
• Deming James Leroy
• Dunning Lucien
• Fahs Brian
• Hairgrove Mark
• Jia Chenghuan
• Mashey John
• Van Dyke James M

Classifications

• G06F12/122

  of the least frequently used [LFU] type, e.g. with individual count value · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F2212/652

  Page size control · CPC title

• G06F12/08 Primary

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title