Optimizing grouping of instructions

Patent metadata

Field	Value
Publication number	US-9766896-B2
Application number	US-201514841805-A
Country	US
Kind code	B2
Filing date	Sep 1, 2015
Priority date	Sep 30, 2014
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Embodiments include optimizing the grouping of instructions in a microprocessor. Aspects include receiving a first clump of instructions from a streaming buffer, pre-decoding each of instructions for select information and sending the instructions to an instruction queue. Aspects further include storing initial grouping information for the instructions in a local register, wherein the initial grouping information is based on the select information. Aspects further include updating the initial group information stored in the local register when additional pre-decode information becomes available and grouping the instructions that are ready to be dispatched into a dispatch group based on the grouping information stored in the local register. Aspects further include dispatching the dispatch group to an issue unit.

First claim

What is claimed is:

1. A method for optimizing grouping of instructions in a microprocessor, the method comprising:
receiving a first clump having a plurality of instructions from a streaming buffer;
pre-decoding each of the plurality of instructions in the first clump for a select information and sending the plurality of instructions to an instruction queue;
storing one or more of the plurality of instructions in a local register and storing an initial grouping information for each of the plurality of instructions in a local register, wherein the initial grouping information is based on the select information;
based on receiving an indication from the instruction queue that one or more of the plurality of instructions is ready to be dispatched from the instruction queue, determining if an additional pre-decode information is available;
based on determining that the additional pre-decode information is not available, grouping the one or more of the plurality of instructions that are ready to be dispatched from the instruction queue into a dispatch group based on the initial grouping information stored in the local register;
based on determining that the additional pre-decode information is available, updating the initial group information stored in the local register based on the additional pre-decode information and grouping the one or more of the plurality of instructions that are ready to be dispatched from the instruction queue into the dispatch group based on the updated grouping information stored in the local register; and
dispatching the dispatch group to an issue unit.

2. The method of claim 1 , wherein the initial grouping information for each of the plurality of instructions is based on worst case grouping scenario.

3. The method of claim 1 , wherein the dispatch group comprises three or less of the plurality of instructions that are ready to be dispatched from the instruction queue.

4. The method of claim 1 , wherein the first clump of instructions is received during a first cycle of the microprocessor and a second clump of instructions having a second plurality of instructions is received from the streaming buffer during a second cycle of the microprocessor.

5. The method of claim 4 , wherein the determination that the additional pre-decode information is available is based off of pre-decoding each of the second plurality of instructions in the second clump.

6. The method of claim 5 , wherein the dispatch group comprises at least one of the first plurality of instruction and at least one of the second plurality of instructions.

7. The method of claim 4 , wherein updating the initial group information includes adding one or more instructions form the second clump to the dispatch group.

Assignees

• IBM

Inventors

• Busaba Fadi Y
• Huffer Michael T
• Hutton David S
• Malley Edward T
• Rell Jr John G
• Schwarz Eric M
• Tsai Aaron

Classifications

• G06F9/3853

  of compound instructions · CPC title

• G06F9/382 Primary

  Pipelined decoding, e.g. using predecoding · CPC title

• G06F9/3016

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F9/3836 Primary

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title