Data processing apparatus and method for pre-decoding instructions to be executed by processing circuitry

Patent metadata

Field	Value
Publication number	US-9348598-B2
Application number	US-201313868186-A
Country	US
Kind code	B2
Filing date	Apr 23, 2013
Priority date	Apr 23, 2013
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A hierarchical cache with at least a unified cache is used to store both instructions and data values, and a further cache coupled between processing circuitry and a unified cache. The unified cache has a plurality of cache lines identified as an instruction cache line or a data cache line. Each data cache line stores at least one data value and the associated information. Pre-decode circuitry is associated with the unified cache and performs a first pre-decode operation on a received instruction for that instruction cache line in order to generate a corresponding partially pre-decoded instruction for storing in the instruction cache line. Further pre-decode circuitry is associated with the further cache, and, when a partially pre-decoded instruction is routed to the further cache, performs a further pre-decode operation on the partially pre-decoded instruction to generate a corresponding pre-decoded instruction for storage in the further cache.

First claim

I claim:

1. A data processing apparatus comprising:
processing circuitry configured to execute instructions fetched from memory in order to perform processing operations on data values;
a hierarchical cache structure configured to store the instructions fetched from said memory for access by the processing circuitry, the hierarchical cache structure comprising at least a unified cache configured to store both instructions and data values and a further cache coupled between the processing circuitry and the unified cache;
the unified cache having a plurality of cache lines, each cache line being identified as an instruction cache line or a data cache line and each cache line having an associated information portion;
each data cache line being configured to store at least one data value and the associated information portion being configured to store error correction code (ECC) data used for error detection and correction within that data cache line's stored content;
pre-decode circuitry configured, for each instruction cache line of the unified cache, to perform a first pre-decode operation on at least one received instruction for that instruction cache line in order to generate at least one partially pre-decoded instruction for storing in that instruction cache line, each at least one partially pre-decoded instruction having more bits than the corresponding received instruction and the unified cache being configured to use the instruction cache line in combination with its associated information portion to store said at least one partially pre-decoded instruction generated by the pre-decode circuitry; and
further pre-decode circuitry configured when the at least one partially pre-decoded instruction stored in one of said instruction cache lines is routed to the further cache for storage within at least one cache line of the further cache, to perform a further pre-decode operation on the at least one partially pre-decoded instruction in order to generate a corresponding at least one pre-decoded instruction for storage in the further cache.

2. A data processing apparatus as claimed in claim 1 , wherein for each instruction cache line the associated information portion is configured to additionally store parity data used for error detection within that instruction cache line's stored content, the parity data comprising less bits than the ECC data.

3. A data processing apparatus as claimed in claim 2 , wherein the parity data comprising m less bits than the ECC data, and the at least one partially pre-decoded instruction generated by the pre-decode circuitry has up to m more bits than the corresponding at least one instruction received by the pre-decode circuitry.

4. A data processing apparatus as claimed in claim 1 , wherein the pre-decode circuitry is configured to modify at least one of the bit values of each received instruction when generating the corresponding partially pre-decoded instruction.

5. A data processing apparatus as claimed in claim 1 , wherein the further pre-decode circuitry is configured to modify at least one of the bit values of each partially pre-decoded instruction when generating the corresponding pre-decoded instruction.

6. A data processing apparatus as claimed in claim 1 , wherein the pre-decode circuitry is configured to generate first pre-decode information associated with each received instruction, such that each partially pre-decoded instruction generated by the pre-decode circuitry comprises the originally received instruction in combination with the first pre-decode information.

7. A data processing apparatus as claimed in claim 6 , wherein the further pre-decode circuitry is configured, for each partially pre-decoded instruction, to generate further pre-decode information based on at least the first pre-decode information of that partially pre-decoded instruction.

8. A data processing apparatus as claimed in claim 7 , wherein each pre-decoded instruction generated by the further pre-decode circuitry comprises the original received instruction and both the first pre-decode information and the further pre-decode information.

9. A data processing apparatus as claimed in claim 7 , wherein the further pre-decode information generated by the further pre-decode circuitry replaces the first pre-decode information and each pre-decoded instruction generated by the further pre-decode circuitry comprises the original received instruction and the further pre-decode information.

10. A data processing apparatus as claimed in claim 1 , wherein each cache line in the unified cache has an identifier field associated therewith whose value is set in order to identify whether the associated cache line is an instruction cache line or a data cache line.

11. A data processing apparatus as claimed in claim 1 , wherein said unified cache is a level two cache, and said further cache is a level one cache.

12. A data processing apparatus as claimed in claim 1 , wherein said further cache is configured to store instructions but not data values.

13. A data processing apparatus as claimed in claim 1 , wherein:
each cache line in the unified cache has an address field associated therewith used to identify a memory address associated with the instructions or data values stored in that cache line;
at least some instructions are modifiable by the processing circuitry and output as data for storage in the memory;
each request for an instruction issued by the processing circuitry is accompanied by an address identifier used to identify the memory address of the instruction being requested;
the unified cache being configured, if no instruction cache line stores a copy of the requested instruction, to also check each data cache line to determine whether the address identifier for the requested instruction matches with the address field of any of the data cache lines, and upon such a match to perform a predetermined operation to output the requested instruction for provision to the processing circuitry.

14. A data processing apparatus as claimed in claim 13 , wherein said predetermined operation comprises flushing from the unified cache the content of the data cache line producing said match, performing a linefill operation to cause that flushed content to be retrieved via the pre-decode circuitry and the resultant generated at least one partially pre-decoded instruction to be stored into one of said instruction cache lines, and outputting the partially pre-decoded instruction corresponding to the requested instruction.

15. A data processing apparatus as claimed in claim 13 , wherein said predetermined operation comprises reading from the unified cache the content of the data cache line producing said match, routing that content to the pre-decode circuitry to cause the first pre-decode operation to be applied to that content, storing the resultant at least one partially pre-decoded instruction generated by the pre-decode circuitry in one of said instruction cache lines, and outputting the partially pre-decoded instruction corresponding to the requested instruction.

16. A method of pre-decoding instructions within a data processing apparatus having processing circuitry for executing instructions fetched from memory in order to perform processing operations on data values, and a hierarchical cache structure for storing the instructions fetched from said memory for access by the processing circuitry, the hierarchical cache structure comprising at least a unified cache configured to store both instructions and data values and a further cache coupled between the processing circuitry and the unified cache, the unified ca

Assignees

• Advanced Risc Mach Ltd

Inventors

• Greenhalgh Peter Richard

Classifications

• G06F9/3802 Primary

  Instruction prefetching · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F9/382

  Pipelined decoding, e.g. using predecoding · CPC title