Electronic device

US9762836B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9762836-B2
Application numberUS-201414510935-A
CountryUS
Kind codeB2
Filing dateOct 9, 2014
Priority dateDec 26, 2013
Publication dateSep 12, 2017
Grant dateSep 12, 2017

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An electronic device comprising a laminated structure including a first semiconductor chip and a second semiconductor chip is disclosed. In one example, the first semiconductor chip includes a sensor portion in which sensors are arranged, and the second semiconductor chip includes a signal processing portion in which signals obtained by the sensors are processed. The signal processing portion includes a high breakdown voltage transistor circuit and a low breakdown voltage transistor circuit. The low breakdown voltage transistor circuit includes a depletion-type field effect transistor.

First claim

Opening claim text (preview).

What is claimed is: 1. An electronic device comprising: a laminated structure including a first semiconductor chip and a second semiconductor chip, the first semiconductor chip including a sensor portion in which sensors are arranged, and the second semiconductor chip including a signal processing portion in which signals obtained by the sensor are processed, wherein respective ones of the sensors include a plurality of transistors, and wherein the signal processing portion includes a depletion-type field effect transistor. 2. An electronic device comprising: a laminated structure including a first semiconductor chip and a second semiconductor chip, the first semiconductor chip including a sensor portion in which sensors are arranged, and the second semiconductor chip including a signal processing portion in which signals obtained by the sensors are processed, wherein respective ones of the sensors include a plurality of transistors, wherein the signal processing portion includes a high breakdown voltage transistor circuit and a low breakdown voltage transistor circuit, and wherein the low breakdown voltage transistor circuit includes a depletion-type field effect transistor. 3. The electronic device according to claim 2 , wherein the high breakdown voltage transistor circuit and the sensor portion overlap each other in a plan view perspective, and wherein in the second semiconductor chip, a light blocking region is formed between the high breakdown voltage transistor circuit and the sensor portion. 4. The electronic device according to claim 2 , wherein the high breakdown voltage transistor circuit and the sensor portion do not overlap each other in a plan view perspective. 5. The electronic device according to claim 2 , wherein the sensors are image sensors, and wherein the electronic device is a solid-state imaging device. 6. The electronic device according to claim 5 , wherein the image sensors are CMOS image sensors. 7. The electronic device according to claim 2 , wherein the depletion-type field effect transistor includes a complete depletion-type SOI structure. 8. The electronic device according to claim 2 , wherein the depletion-type field effect transistor includes a partial depletion-type SOI structure. 9. The electronic device according to claim 2 , wherein the depletion-type field effect transistor includes a fin structure. 10. The electronic device according to claim 2 , wherein the depletion-type field effect transistor includes a deeply depleted channel structure. 11. The electronic device according to claim 2 , wherein at least one of the signal processing portion and the low breakdown voltage transistor circuit includes an analog-digital converter, and wherein the analog-digital converter includes the depletion-type field effect transistor. 12. The electronic device according to claim 11 , wherein the analog-digital converter includes at least one of a single slope-type analog-digital converter, a successive approximation-type analog-digital converter, and a delta-sigma modulation-type analog-digital converter. 13. The electronic device according to claim 11 , wherein the analog-digital converter includes a gray code counter. 14. The electronic device according to claim 11 , wherein the analog-digital converter is provided with respect to a plurality of the sensors, wherein the analog-digital converter is a single slope-type analog-digital converter and includes a ramp voltage generator, a comparator to which an analog signal obtained by the sensor and a ramp voltage from the ramp voltage generator are input, and a counter portion to which a clock is supplied from a clock supply portion and which operates based on an output signal of the comparator, and wherein the counter portion includes the depletion-type field effect transistor. 15. The electronic device according to claim 14 , wherein the clock supply portion includes the depletion-type field effect transistor. 16. The electronic device according to claim 11 , wherein the signal processing portion or the low breakdown voltage transistor circuit includes a clock supply portion which is connected to the analog-digital converter, and wherein the clock supply portion has the depletion-type field effect transistor. 17. The electronic device according to claim 16 , wherein the clock supply portion includes a PLL circuit. 18. The electronic device according to claim 2 , wherein the second semiconductor chip includes a memory portion. 19. The electronic device according to claim 2 , further comprising: a third semiconductor chip that is provided with a memory portion, wherein the first, second and third semiconductor chips are laminated in the order of the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip. 20. The electronic device according to claim 13 , wherein the gray code counter includes the depletion-type field effect transistor.

Assignees

Inventors

Classifications

  • Package configurations · CPC title

  • H04N25/79Primary

    Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

  • Electricity · mapped topic

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Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9762836B2 cover?
An electronic device comprising a laminated structure including a first semiconductor chip and a second semiconductor chip is disclosed. In one example, the first semiconductor chip includes a sensor portion in which sensors are arranged, and the second semiconductor chip includes a signal processing portion in which signals obtained by the sensors are processed. The signal processing portion i…
Who is the assignee on this patent?
Sony Corp
What technology area does this patent fall under?
Primary CPC classification H04N25/79. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 12 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).