Amplifying circuit, AD converter, integrated circuit, and wireless communication apparatus

Patent metadata

Field	Value
Publication number	US-9762218-B2
Application number	US-201615092977-A
Country	US
Kind code	B2
Filing date	Apr 7, 2016
Priority date	May 12, 2015
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

An amplifying circuit according to an embodiment includes an input terminal, an output terminal, first and second operational amplifiers, first and second input impedance elements, first to third feedback impedance elements, and an adder. The first (second) operational amplifier includes an inversion input terminal connected to a first (third) node and an output terminal connected to a second (fourth) node. The first (second) input impedance element has one end connected to the input terminal and the other end connected to the first (third) node. The first (second) feedback impedance element has one end connected to the first (third) node and the other end connected to the second (fourth) node. The third feedback impedance element has one end connected to the first node and the other end connected to the fourth node. The adder adds output voltages of the first and second operational amplifiers.

First claim

The invention claimed is:

1. An amplifying circuit comprising:
an input terminal to receive an input voltage;
an output terminal to output an output voltage;
a first operational amplifier including an inversion input terminal connected to a first node, a non-inversion input terminal, and an output terminal connected to a second node;
a first input impedance element having one end connected to the input terminal and another end connected to the first node;
a first feedback impedance element having one end connected to the first node and another end connected to the second node;
a second operational amplifier including an inversion input terminal connected to a third node, a non-inversion input terminal, and an output terminal connected to a fourth node;
a second input impedance element having one end connected to the input terminal and another end connected to the third node;
a second feedback impedance element having one end connected to the third node and another end connected to the fourth node;
a third feedback impedance element having one end connected to the first node and another end connected to the fourth node; and
an adder to add an output voltage of the first operational amplifier and an output voltage of the second operational amplifier and outputs an added output voltage.

2. The amplifying circuit according to claim 1 ,
wherein the first input impedance element is a first sample-and-hold circuit to sample the input voltage, and
the second input impedance element is a second sample-and-hold circuit to sample the input voltage.

3. The amplifying circuit according to claim 1 ,
wherein the first feedback impedance element, the second feedback impedance element, and the third feedback impedance element are capacitative elements.

4. The amplifying circuit according to claim 1 ,
wherein the adder includes
a third operational amplifier including an inversion input terminal connected to a fifth node, a non-inversion input terminal, and an output terminal connected to the output terminal of the amplifying circuit,
a third input impedance element having one end connected to the second node and another end connected to the fifth node,
a fourth input impedance element having one end connected to the fourth node and another end connected to the fifth node, and
a fourth feedback impedance element having one end connected to the fifth node and another end connected to the output terminal of the amplifying circuit.

5. The amplifying circuit according to claim 1 , further comprising:
a fourth operational amplifier including an inversion input terminal connected to a sixth node, a non-inversion input terminal, and an output terminal connected to the output terminal of the amplifying circuit;
a fifth input impedance element having one end connected to the second node and another end connected to the sixth node;
a sixth input impedance element having one end connected to the fourth node and another end connected to the sixth node;
a fifth feedback impedance element having one end connected to the sixth node and another end connected to the output terminal of the amplifying circuit; and
a sixth feedback impedance element having one end connected to the fifth node and another end connected to the output terminal of the amplifying circuit.

6. The amplifying circuit according to claim 4 ,
wherein the third input impedance element is a third sample-and-hold circuit to sample the output voltage of the first operational amplifier, and
the fourth input impedance element is a fourth sample-and-hold circuit to sample the output voltage of the second operational amplifier.

7. The amplifying circuit according to claim 4 ,
wherein the fourth feedback impedance element is a capacitative element.

8. The amplifying circuit according to claim 1 ,
wherein the adder includes
a third sample-and-hold circuit to sample the output voltage of the first operational amplifier,
a first AD converter to execute AD conversion on a voltage held by the third sample-and-hold circuit,
a fourth sample-and-hold circuit to sample the output voltage of the second operational amplifier,
a second AD converter to execute AD conversion on a voltage held by the fourth sample-and-hold circuit, and
a digital adder to add output signals of the first AD converter and the second AD converter.

9. The amplifying circuit according to claim 1 ,
wherein the adder includes
a buffer circuit to invert the output voltage of the first operational amplifier and outputs an output voltage, and
a fifth sample-and-hold circuit to sample the output voltage of the second operational amplifier and the output voltage of the buffer circuit.

10. The amplifying circuit according to claim 9 ,
wherein the amplifying circuit has a differential configuration.

11. An AD converter comprising the amplifying circuit according to claim 1 .

12. An integrated circuit comprising the AD converter according to claim 11 .

13. A wireless communication apparatus comprising the integrated circuit according to claim 12 .

Assignees

• Toshiba Kk

Inventors

• Matsuno Junya
• Furuta Masanori
• Itakura Tetsuro

Classifications

• H03F3/45183

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03F2203/45138

  Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers · CPC title

• H03K5/02 Primary

  by amplifying (H03K5/04 takes precedence) · CPC title

• G11C27/026

  associated with an amplifier (G11C27/028 takes precedence) · CPC title