Apparatus and methods for equalization

Patent metadata

Field	Value
Publication number	US-9319004-B2
Application number	US-201213684904-A
Country	US
Kind code	B2
Filing date	Nov 26, 2012
Priority date	Nov 26, 2012
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

Apparatus and methods for equalization are provided. In certain implementations, an equalizer includes first and second feedback resistors, first and second equalization resistors, an equalization capacitor, and an amplification circuit that includes first to fourth input terminals and first and second output terminals. The amplification circuit can receive a differential input voltage signal between the first and third input terminals, and the first and second equalization resistors and the equalization capacitor are electrically connected in series between the second and fourth input terminals with the equalization capacitor between the first and second equalization resistors. Additionally, the first feedback resistor is electrically connected between the first output terminal and the second input terminal, and the second feedback resistor is electrically connected between the second output terminal and the fourth input terminal.

First claim

What is claimed is:

1. An apparatus, comprising:
a first equalizer configured to receive an input signal and to generate an equalized signal;
a gain circuit configured to receive the equalized signal from the first equalizer and to amplify the equalized signal to generate a differential input signal; and
a second equalizer, comprising:
means for amplifying including a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a common-mode reference voltage terminal configured to receive a common-mode reference voltage signal, a first output terminal, and a second output terminal, wherein the amplification means is configured to receive the differential input signal between the first and third input terminals and to generate a differential output signal between the first and second output terminals, wherein the amplification means is configured to control a voltage of the first output terminal based on a voltage difference between the first and second input terminals, wherein the amplification means is further configured to control a voltage of the second output terminal based on a voltage difference between the third and fourth input terminals, wherein the amplification means is further configured to control a common-mode voltage of the differential output signal based on the common-mode reference voltage signal;
a first feedback resistor electrically connected between the first output terminal and the second input terminal of the amplification means;
a second feedback resistor electrically connected between the second output terminal and the fourth input terminal of the amplification means;
a first equalization resistor;
a second equalization resistor; and
an equalization capacitor, wherein the first and second equalization resistors and the equalization capacitor are electrically connected in series between the second and fourth input terminals of the amplification means.

2. The apparatus of claim 1 , wherein the equalization capacitor is disposed in an electrical path between the first and second equalization resistors.

3. The apparatus of claim 2 , wherein the equalization capacitor is programmable, and wherein the first and second equalization resistors are programmable.

4. The apparatus of claim 3 , wherein the first and second feedback resistors are programmable.

5. The apparatus of claim 1 , further comprising a first feedback capacitor electrically connected between the first output terminal and the second input terminal of the amplification means and a second feedback capacitor electrically connected between the second output terminal and the fourth input terminal of the amplification means.

6. An apparatus, comprising:
a first equalizer configured to receive an input signal and to generate an equalized signal;
a gain circuit configured to receive the equalized signal from the first equalizer and to amplify the equalized signal to generate a differential input signal; and
a second equalizer configured to receive the differential input signal from the gain circuit, the second equalizer comprising:
an amplification circuit including a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a common-mode reference voltage terminal configured to receive a common-mode reference voltage signal, a first output terminal, and a second output terminal, wherein the amplification circuit is configured to receive the differential input signal between the first and third input terminals and to generate a differential output signal between the first and second output terminals, wherein the amplification circuit is configured to control a voltage of the first output terminal based on a voltage difference between the first and second input terminals, wherein the amplification circuit is further configured to control a voltage of the second output terminal based on a voltage difference between the third and fourth input terminals, and wherein the amplification circuit is further configured to control a common-mode voltage of the differential output signal based on the common-mode reference voltage signal;
a first feedback resistor electrically connected between the first output terminal and the second input terminal of the amplification circuit;
a second feedback resistor electrically connected between the second output terminal and the fourth input terminal of the amplification circuit;
a first equalization resistor;
a second equalization resistor; and
an equalization capacitor, wherein the first and second equalization resistors and the equalization capacitor are electrically connected in series between the second and fourth input terminals of the amplification circuit.

7. The apparatus of claim 6 , wherein the equalization capacitor is disposed in an electrical path between the first and second equalization resistors.

8. The apparatus of claim 7 , wherein the equalization capacitor is programmable.

9. The apparatus of claim 7 , wherein the first and second equalization resistors are programmable.

10. The apparatus of claim 7 , wherein the first and second feedback resistors are programmable.

11. The apparatus of claim 6 , further comprising:
a downconverter configured to receive a radio frequency receive signal and to downshift the radio frequency receive signal to generate the differential input signal.

12. The apparatus of claim 11 , further comprising:
an analog-to-digital converter configured to receive the differential output signal and to generate a digital signal.

13. The apparatus of claim 6 , wherein the input signal comprises a distance related frequency component and a velocity related frequency component.

14. The apparatus of claim 13 , wherein the first and second equalizers are configured to boost the distance related frequency component by a frequency dependent gain.

15. The apparatus of claim 6 , wherein the second equalizer further comprises a first feedback capacitor electrically connected between the first output terminal and the second input terminal of the amplification circuit and a second feedback capacitor electrically connected between the second output terminal and the fourth input terminal of the amplification circuit.

16. The apparatus of claim 6 , wherein the amplification circuit comprises:
a first differential amplifier including a non-inverting input terminal configured to operate as the first input terminal of the amplification circuit, an inverting input terminal configured to operate as the second input terminal of the amplification circuit, and an output terminal configured to operate as the first output terminal of the amplification circuit; and
a second differential amplifier including a non-inverting input terminal configured to operate as the third input terminal of the amplification circuit, an inverting input terminal configured to operate as the fourth input terminal of the amplification circuit, and an output terminal configured to operate as the second output terminal of the amplification circuit.

17. The apparatus of claim 6 , wherein the first equalizer is a passive equalizer.

18. The apparatus of claim 6 , wherein the amplification circuit comprises feedback circuitry that controls the common-mode output voltage of the differential output signal to be about equal to the common-mode reference voltage signal.

19. The apparatus of claim 6 , further comprising a band-gap voltage reference circuit configured to generate the common-mode reference voltage signal.

Assignees

• Analog Devices Inc

Inventors

• Bandyopadhyay Abhishek
• Foley David Paul

Classifications

• H03F2203/45134

  the whole differential amplifier together with other coupled stages being fully differential realised · CPC title

• H03F2203/45522

  the FBC comprising one or more potentiometers · CPC title

• H03F2203/45138

  Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers · CPC title

• H03F2203/45526

  the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC · CPC title

• H03F1/34 Primary

  Negative-feedback-circuit arrangements with or without positive feedback (H03F1/02 - H03F1/30, H03F1/38 - H03F1/50, H03F3/50 take precedence {; for rejection of common mode signals H03F3/45479}) · CPC title