Semiconductor device and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-9761718-B2
Application number	US-38981909-A
Country	US
Kind code	B2
Filing date	Feb 20, 2009
Priority date	Mar 7, 2008
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A semiconductor device includes: a sidewall insulating film; a gate electrode; source and drain regions; a first stress film; and a second stress film.

First claim

What is claimed is:

1. A semiconductor device comprising:
a sidewall insulating film on a semiconductor substrate;
a gate electrode formation trench inside the sidewall insulating film;
a gate electrode inside the gate electrode formation trench;
source and drain regions in the semiconductor;
a first stress film outside of the gate electrode but not on or extending over an upper surface of the gate electrode, the first stress film having a stress type; and
a second stress film outside the first stress film but not on or extending over the upper surface of the gate electrode, the first and second stress films having the same stress type,
wherein,
each of the first stress film and the second stress film has etch resistance against an etching species used in etching of a silicon oxide film,
the first stress film has a higher film density and a greater etch resistance against the etching species than the second stress film, and
the first stress film and the second stress film are each formed of the same material, although an amount of an additive may differ.

2. The semiconductor device according to claim 1 , wherein
the first stress film and the second stress film are each formed of a silicon nitride film, and
film density of the first stress film is higher than film density of the second stress film.

3. The semiconductor device according to claim 1 , wherein
the first stress film and the second stress film are each formed of a silicon nitride film that has compressive stress and contains carbon,
the first stress film contains carbon at a ratio in a range of 6 atomic % to 8 atomic %, and
the second stress film contains carbon at a ratio that is at least 1 atomic % and lower than 6 atomic %.

4. The semiconductor device according to claim 1 , wherein
the first stress film and the second stress film are each formed of a silicon nitride film that has tensile stress and contains hydrogen,
the first stress film contains hydrogen at a ratio lower than 12 atomic %, and
the second stress film contains hydrogen at a ratio in a range of 12 atomic % to 25 atomic %.

5. The semiconductor device according to claim 1 , wherein the first stress film has a thickness within the range of 5 nm to 30 nm, both inclusive.

6. The semiconductor device according to claim 1 , wherein the first stress film is in contact with the source and drain regions in the semiconductor substrate on both sides of the gate electrode.

7. The semiconductor device according to claim 1 , wherein, the second stress film is not in direct contact with the source and drain regions in the semiconductor substrate on both sides of the gate electrode.

8. The semiconductor device according to claim 1 further comprising a silicide region on each source and drain region, wherein the first stress film is on the silicide region.

9. The semiconductor device according to claim 1 wherein the first stress film is in-between the second stress film and the substrate.

10. The semiconductor device according to claim 1 ,
wherein the first stress film and the second stress film are each formed of a silicon nitride film.

11. The semiconductor device according to claim 1 , wherein a gate insulating film is inside of the side wall insulating film.

12. The semiconductor device according to claim 11 ,
wherein the gate insulating film is between the gate electrode and the side wall insulating film.

13. The semiconductor device according to claim 1 ,
wherein a gate insulating film is between an element formation region and the gate electrode.

Assignees

• Miyanami Yuki
• Sony Corp

Inventors

• Miyanami Yuki

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10W20/097

  by thermally treating · CPC title

• H10W20/095

  by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096) · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title