Semiconductor device with embedded non-volatile memory and method of fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-9761680-B2
Application number	US-201514923409-A
Country	US
Kind code	B2
Filing date	Oct 26, 2015
Priority date	Oct 26, 2015
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

The present invention provides a semiconductor device, including a substrate with a memory region and a logic region, the substrate having a recess disposed in the memory region, a logic gate stack disposed in the logic region, and a non-volatile memory disposed in the recess. The non-volatile memory includes at least two floating gates and at least two control gates disposed on the floating gates, where each floating gate has a step-shaped bottom, and the step-shaped bottom includes a first bottom surface and a second bottom surface lower than the first bottom surface.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate with a memory region and a logic region, the substrate having a recess disposed in the memory region;
a logic gate stack disposed in the logic region; and
a non-volatile memory disposed in the recess, the non-volatile memory comprising at least two floating gates and at least two control gates disposed on the floating gates, wherein each floating gate has a step-shaped bottom and a flat top surface, wherein the flat top surface of each floating gate is not a step-shaped surface, and the step-shaped bottom includes a first bottom surface and a second bottom surface lower than the first bottom surface, in addition, each control gate disposed on the flat top surface of the floating gate, and each control gate has a flat bottom surface.

2. The semiconductor device according to claim 1 , wherein the non-volatile memory includes an oxide-nitride-oxide (ONO) stack-layer between the control gate and the floating gate.

3. The semiconductor device according to claim 1 , wherein a top surface of the control gate is lower than a top surface of the substrate.

4. The semiconductor device according to claim 1 , wherein a top surface of the control gate and a top surface of the substrate are on a same level.

5. The semiconductor device according to claim 1 , further comprising an erase gate, wherein the erase gate partially overlaps the two floating gate.

6. The semiconductor device according to claim 1 , further comprising at least two cap layers disposed on each control gate, wherein a top surface of the cap layer is lower than a top surface of the logic gate stack.

7. The semiconductor device according to claim 6 , wherein a vertical distance between a top surface of the substrate and the top surface of the cap layer is lower than 700 angstroms.

8. The semiconductor device according to claim 1 , further comprising at least one shallow trench isolation (STI) disposed in the substrate.

9. The semiconductor device according to claim 8 , wherein the step-shaped bottom of each floating gate is lower than a bottom surface of the STI.

10. The semiconductor device according to claim 1 , wherein the floating gate is composed of a lower polysilicon layer.

Assignees

• United Microelectronics Corp

Inventors

• Li Dongdong
• Chen Ko-Chi
• Wang Shen-De

Classifications

• H01L29/42328 Primary

  Electricity · mapped topic

• H01L29/42336

  Electricity · mapped topic

• H01L27/11534

  Electricity · mapped topic

• H01L29/66825

  Electricity · mapped topic

• H10D30/6894

  having one gate at least partly in a trench · CPC title