Method of manufacturing an integrated circuit having field effect transistors including a peak in a body dopant concentration

Patent metadata

Field	Value
Publication number	US-9761665-B2
Application number	US-201615157448-A
Country	US
Kind code	B2
Filing date	May 18, 2016
Priority date	Mar 12, 2009
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a first FET and a second FET,
wherein at least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET,
at least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively;
a dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel; and
the dopant concentration of the body of each of the first and second FETs has multiple peaks along the channel.

2. The integrated circuit of claim 1 , wherein the dopant concentration of the body of each of the first and second FETs is declining along the channel from the peak location to a pn junction between body and source.

3. The integrated circuit of claim 1 , wherein the dopant concentration of the body of each of the first and second FETs is declining from the peak location to the drain.

4. The integrated circuit of claim 1 , wherein a fraction of a channel area of each of the first and second FETs having a dopant concentration of the body of at least 95% of a value at the peak location to an overall channel area of the respective FET is at least 15%.

5. The integrated circuit of claim 1 , wherein the multiple peaks have a same maximum dopant concentration.

6. The integrated circuit of claim 1 , wherein the first FET is a power FET and the second FET is a sense FET having an area that is smaller than the area of the power FET.

7. The integrated circuit of claim 1 , comprising:
wherein the gate of the first FET is connected to the gate of the second FET;
one of source and drain of the first FET is connected to the corresponding one of source and drain of the second FET; and
wherein the other one of source and drain of the first FET and the other one of source and drain of the second FET are connected to the circuit element.

8. The integrated circuit of claim 1 , wherein a profile of the dopant concentration of the body of the first FET and a profile of the dopant concentration of the body of the second FET follow substantially similar contours along the channel of the first and second FETs, respectively.

9. The integrated circuit of claim 1 , wherein, at an intersection of a profile of the dopant concentration of the body and a profile of the dopant concentration of the source of each of the first and second FETs, the profile of the dopant concentration of the body declines into the source and the profile of the dopant concentration of the source declines into the body.

10. The integrated circuit of claim 1 , wherein each of the first and second FETs is a trench FET or a lateral FET.

11. A method of forming the integrated circuit of claim 1 , comprising:
forming a first FET and a second FET;
electrically connecting at least one of source, drain, gate of the first FET to the corresponding one of source, drain, gate of the second FET; and
connecting at least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET to a circuit element, respectively; and
wherein the formation of the first and second FET includes forming a body of each of the first and second FETs having a dopant concentration along a channel of the respective FET that includes a peak at a peak location within the channel; and
formation of the body of each of the first and second FETs includes implanting the dopants into the semiconductor substrate at different implant energies such that multiple peak concentrations of the implanted dopants are deeper within the substrate than the pn junction between source and body.

12. The method of claim 11 , wherein forming the first and second FETs as lateral FETs, and forming the body of each of the first and second FETs includes implanting dopants into an area of a semiconductor substrate; the method further comprising:
forming a gate dielectric and a gate electrode at least partly on the area of the semiconductor substrate.

13. The method of claim 11 , wherein forming the body of each of the first and second FETs includes:
implanting dopants into a semiconductor substrate and annealing implant damages such that a fraction of a channel area of each of the first and second FETs having a dopant concentration of at least 95% of a value at the peak location to an overall channel area of the respective FET is at least 15%.

14. The method of claim 11 , further comprising:
forming the first FET as a power FET and forming the second FET as a sense FET having an area that is smaller than the area of the power FET.

15. The method of claim 11 , further comprising:
connecting the gate of the first FET to the gate of the second FET;
connecting one of source and drain of the first FET to the corresponding one of source and drain of the second FET; and
connecting the other one of source and drain of the first FET and the other one of source and drain of the second FET to the circuit element.

16. The integrated circuit of claim 11 , wherein a profile of the dopant concentration of the body of the first FET and a profile of the dopant concentration of the body of the second FET follow substantially similar contours along the channel of the first and second FETs, respectively.

17. The integrated circuit of claim 11 , wherein, at an intersection of a profile of the dopant concentration of the body and a profile of the dopant concentration of the source of each of the first and second FETs, the profile of the dopant concentration of the body declines into the source and the profile of the dopant concentration of the source declines into the body.

18. The integrated circuit of claim 11 , wherein each of the first and second FETs is a trench FET.

Assignees

• Infineon Technologies Ag

Inventors

• Meyer Thorsten
• Decker Stefan
• Krischke Norbert
• Kadow Christoph

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H01L29/66537

  Electricity · mapped topic

• H01L29/4236

  Electricity · mapped topic