Method for manufacturing array substrate, array substrate and display device

Patent metadata

Field	Value
Publication number	US-9761617-B2
Application number	US-201615106052-A
Country	US
Kind code	B2
Filing date	Jan 14, 2016
Priority date	Jul 17, 2015
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A method for manufacturing an array substrate comprises: forming a pixel electrode and a gate of a thin film transistor on a substrate; forming a gate insulating layer; forming an active layer and a source and a drain, which are provided on the active layer, of the thin film transistor by a patterning process; forming a passivation layer; forming a main via penetrating through the gate insulating layer and the passivation layer and a main-via extension portion under a portion of the drain by a patterning process, wherein the main via is connected to the main-via extension portion; removing a portion of the drain which protrudes above the main-via extension portion so as to form a final via; and forming a connection electrode and a common electrode, wherein the connection electrode electrically connects the drain to the pixel electrode through the final via.

First claim

What is claimed is:

1. A method for manufacturing an array substrate, comprising:
step S1, forming a pattern comprising a pixel electrode on a substrate;
step S2, forming a pattern comprising a gate of a thin film transistor on the substrate after the step S1;
step S3, forming a gate insulating layer on the substrate after the step S2;
step S4, forming a pattern comprising an active layer and a source and a drain, which are provided on the active layer, of the thin film transistor on the substrate by a patterning process after the step S3;
step S5, forming a passivation layer on the substrate after the step S4;
step S6, forming, on the substrate, a pattern comprising a main via penetrating through the gate insulating layer and the passivation layer and a main-via extension portion under a portion of the drain by a patterning process after the step S5, wherein the main via is connected to the main-via extension portion;
step S7, removing a portion of the drain which protrudes above the main-via extension portion after the step S6, so as to form a pattern comprising a final via; and
step S8, forming a pattern comprising a connection electrode and a common electrode on the substrate after the step S7, wherein the connection electrode electrically connects the drain to the pixel electrode through the final via.

2. The method for manufacturing an array substrate according to claim 1 , wherein, the array substrate comprises a thin film transistor region, a common electrode region and a via region between the thin film transistor region and the common electrode region, and the step S6 comprises steps of:
forming a layer of first photoresist on the substrate on which the passivation layer is formed;
exposing the layer of first photoresist with a halftone mask or a grayscale mask such that the layer of first photoresist is divided into a first photoresist completely removed region, a first photoresist completely remaining region and a first photoresist partially remaining region, wherein, the first photoresist completely removed region corresponds to a central portion of the via region, the first photoresist partially remaining region corresponds to a portion, which is close to the via region, of a drain region of the thin film transistor region and a peripheral region, which is close to the thin film transistor region, of the via region, and the first photoresist completely remaining region corresponds to the remaining region; after development is performed, a thickness of the first photoresist in the first photoresist completely remaining region remains unchanged, the first photoresist in the first photoresist completely removed region is removed completely, and a thickness of the first photoresist in the first photoresist partially remaining region is decreased;
removing portions, which are under the first photoresist completely removed region, of the passivation layer and the gate insulating layer by an etching process;
removing, by an ashing process, the first photoresist in the first photoresist partially remaining region, so as to expose a portion of the passivation layer under the first photoresist partially remaining region and the peripheral region of the via region close to the thin film transistor region;
removing portions, which are under the first photoresist partially remaining region, of the passivation layer, the active layer and the gate insulating layer by an etching process, so as to form the pattern comprising the main via and the main-via extension portion; and
removing the remaining first photoresist.

3. The method for manufacturing an array substrate according to claim 2 , wherein, the layer of first photoresist has a thickness ranging from 2.2 μm to 2.5 μm.

4. The method for manufacturing an array substrate according to claim 2 , wherein, both the step of removing portions, which are under the first photoresist completely removed region, of the passivation layer and the gate insulating layer by an etching process and the step of removing portions, which are under the first photoresist partially remaining region, of the passivation layer, the active layer and the gate insulating layer by an etching process are each performed by a dry etching process.

5. The method for manufacturing an array substrate according to claim 1 , wherein, the step S7 comprises a step of:
removing, on the substrate provided with the pattern comprising the main via and the main-via extension portion, the portion of the drain which protrudes above the main-via extension portion so as to form the pattern comprising the final via by a single patterning process.

6. The method for manufacturing an array substrate according to claim 1 , wherein, the step S8 comprises steps of:
forming a transparent conductive film, and forming the pattern comprising the connection electrode and the common electrode by a single patterning process.

7. The method for manufacturing an array substrate according to claim 1 , wherein, the common electrode region comprises a first region and a second region arranged alternately, and the step S8 comprises steps of:
forming a layer of second photoresist on the substrate provided with the pattern comprising the main via and the main-via extension portion;
exposing the layer of second photoresist with a halftone mask or a grayscale mask such that the layer of second photoresist is divided into a second photoresist completely removed region, a second photoresist completely remaining region and a second photoresist partially remaining region, wherein, the second photoresist completely removed region corresponds to a source region of the thin film transistor region, the via region and the second region of the common electrode region, the second photoresist partially remaining region corresponds to a drain region of the thin film transistor region, and the second photoresist completely remaining region corresponds to the remaining region comprising the first region; after development is performed, a thickness of the second photoresist in the second photoresist completely remaining region remains unchanged, the second photoresist in the second photoresist completely removed region is removed completely, and a thickness of the second photoresist in the second photoresist partially remaining region is decreased;
removing a portion, which protrudes above the main-via extension portion, of the drain by an etching process, so as to form the pattern comprising the final via;
removing, by an ashing process, the second photoresist in the second photoresist partially remaining region;
forming a transparent conductive film on the substrate after the step of removing, by an ashing process, the second photoresist in the second photoresist partially remaining region; and
removing the remaining second photoresist by a stepped stripping process, and forming the pattern comprising the connection electrode and the common electrode.

8. The method for manufacturing an array substrate according to claim 7 , wherein, the layer of second photoresist has a thickness ranging from 2.5 μm to 3.0 μm.

9. The method for manufacturing an array substrate according to claim 1 , wherein, the step S4 comprises steps of:
depositing an active-layer film and a source-drain metal film sequentially; and
forming the pattern comprising the active layer and the source and the drain, which are provided on the active layer, of the thin film transistor by a single patterning process using a grayscale mask or a halftone mask.

10. The method for manufacturing an array substrate according to claim 1 , wherein, the step S4 comprises steps of:
depositing an active-layer film, and forming a pattern comprising the active layer of the thin film tr

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Liu Zheng
• Kuo Tsung Chieh
• Chen Xi
• Zhang Xiaoxiang
• Zhang Zhichao
• Liu Mingxuan

Classifications

• G02F1/134309

  characterised by their geometrical arrangement · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F2201/121

  common or background · CPC title

• H01L27/1288 Primary

  Electricity · mapped topic

• H01L29/66765

  Electricity · mapped topic