Hardmask for a halo/extension implant of a static random access memory (SRAM) layout

Patent metadata

Field	Value
Publication number	US-9761594-B2
Application number	US-201314043871-A
Country	US
Kind code	B2
Filing date	Oct 2, 2013
Priority date	Oct 2, 2013
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

Approaches for providing a hardmask used during a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device are disclosed. Specifically, approaches are provided for forming a pull-down (PD) transistor over a substrate; forming a pass-gate (PG) transistor over the substrate; and patterning a hardmask over the device, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor, wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor. The respective distances between the first section and the PD transistor, and the second section and the PG transistor, are selected to prevent a halo/extension implant from impacting one side of the PD transistor, while allowing the halo/extension implant to impact both sides of the PG transistor.

First claim

What is claimed is:

1. A method for forming a hardmask for a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device, the method comprising:
forming a pull-down (PD) transistor over a substrate;
forming a pass-gate (PG) transistor over the substrate;
patterning a hardmask over the device after forming the PD transistor and forming the PG transistor, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor;
providing a distance between the first section and the PD transistor to prevent a halo/extension implant from impacting a first side of the PD transistor; and
implanting the semiconductor device with the halo/extension implant, wherein the halo/extension implant comprises a first implant at a first angle and a second implant at a second angle
wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor, and
wherein the second section of the hardmask is patterned to allow the first implant to impact the following: the first side of the PD transistor, a second side of the PD transistor, a first side of the PG transistor, and a second side of the PG transistor, and wherein the second section of the hardmask is patterned to allow the second implant to impact the following: the first side of the PD transistor, the second side of the PD transistor, the first side of the PG transistor, and the second side of the PG transistor.

2. The method according to claim 1 , further comprising forming a set of fins from the substrate, wherein the PG transistor and the PD transistor are formed over the set of fins.

3. A method for forming a hardmask for a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device, the method comprising:
forming a pull-down (PD) transistor over a substrate;
forming a pass-gate (PG) transistor over the substrate;
patterning a hardmask over the device after forming the PD transistor and forming the PG transistor, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor;
providing a distance between the first section and the PD transistor to prevent a halo/extension implant from impacting a first side of the PD transistor; and
implanting the semiconductor device with the halo/extension implant, wherein the halo/extension implant comprises a first implant at a first angle and a second implant at a second angle
wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor, and
wherein the first section of the hardmask is patterned to allow the first implant to impact the following: the first side of the PD transistor, a second side of the PD transistor, a first side of the PG transistor, and a second side of the PG transistor, and wherein the first section of the hardmask is patterned to allow the second implant to impact only the following: the second side of the PD transistor, the first side of the PG transistor, and the second side of the PG transistor.

4. The method according to claim 3 , further comprising forming a set of fins from the substrate, wherein the PG transistor and the PD transistor are formed over the set of fins.

5. A method for forming a hardmask for a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device, the method comprising:
forming a pull-down (PD) transistor over a substrate;
forming a pass-gate (PG) transistor over the substrate;
patterning a hardmask over the device, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor, wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor;
providing a distance between the first section and the PD transistor to prevent a halo/extension implant from impacting a first side of the PD transistor; and
implanting the semiconductor device with the halo/extension implant, wherein the halo/extension implant comprises a first implant at a first angle and a second implant at a second angle;
wherein the second section of the hardmask is patterned to allow the first implant to impact the following: the first side of the PD transistor, a second side of the PD transistor, a first side of the PG transistor, and a second side of the PG transistor, and wherein the second section of the hardmask is patterned to allow the second implant to impact the following: the first side of the PD transistor, the second side of the PD transistor, the first side of the PG transistor, and the second side of the PG transistor.

6. The method according to claim 5 , further comprising forming a set of fins from the substrate, wherein the PG transistor and the PD transistor are formed over the set of fins.

7. A method for forming a hardmask for a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device, the method comprising:
forming a pull-down (PD) transistor over a substrate;
forming a pass-gate (PG) transistor over the substrate;
patterning a hardmask over the device, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor, wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor;
providing a distance between the first section and the PD transistor to prevent a halo/extension implant from impacting a first side of the PD transistor; and
implanting the semiconductor device with the halo/extension implant, wherein the halo/extension implant comprises a first implant at a first angle and a second implant at a second angle;
wherein the first section of the hardmask is patterned to allow the first implant to impact the following: the first side of the PD transistor, a second side of the PD transistor, a first side of the PG transistor, and a second side of the PG transistor, and wherein the first section of the hardmask is patterned to allow the second implant to impact only the following: the second side of the PD transistor, the first side of the PG transistor, and the second side of the PG transistor.

8. The method according to claim 7 , further comprising forming a set of fins from the substrate, wherein the PG transistor and the PD transistor are formed over the set of fins.

Assignees

• Globalfoundries Inc

Inventors

• Wu Xusheng
• Liu Bingwu
• Mann Randy

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/22

  using masks · CPC title

• H01L29/785

  Electricity · mapped topic

• H01L27/1104 Primary

  Electricity · mapped topic

• H01L21/26586

  Electricity · mapped topic