Interconnect layer and method for manufacturing the same
US-2024420994-A1 · Dec 19, 2024 · US
US9048293B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9048293-B2 |
| Application number | US-201414253409-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 15, 2014 |
| Priority date | Jan 26, 2011 |
| Publication date | Jun 2, 2015 |
| Grant date | Jun 2, 2015 |
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A semiconductor device and a method for manufacturing the same are disclosed. An additional spacer is formed at a lateral surface of an upper part of the bit line so that the distance of insulation films between a storage node and a neighboring storage node contact plug is increased. Accordingly, the distance between the storage node and the neighboring storage node contact is guaranteed and a bridge failure is prevented.
Opening claim text (preview).
What is claimed is: 1. A method for manufacturing a semiconductor device comprising: forming a bit line over a semiconductor substrate; forming a first conductive pattern over a first sidewall of the bit line, the first conductive pattern including a first lower pattern and a first upper pattern; forming a second conductive pattern over a second sidewall of the bit line; forming a first spacer between the first sidewall of the bit line and the first upper pattern; forming…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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