Interposer, semiconductor package with the same and method for preparing a semiconductor package with the same

Patent metadata

Field	Value
Publication number	US-9761535-B1
Application number	US-201615194195-A
Country	US
Kind code	B1
Filing date	Jun 27, 2016
Priority date	Jun 27, 2016
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

One aspect of the present disclosure provides an interposer for a semiconductor package. The interposer includes a substrate portion and a wall portion disposed on the substrate portion. The substrate portion has a first side, a second side, and an electrical interconnect structure between the first side and the second side. The substrate portion is substantially free from conductive through vias, and the cost for fabricating through silicon vias (TSV) is very expensive; therefore, the fabrication cost of the interposer can be dramatically reduced. In addition, the wall portion is disposed on the first side and defining an aperture exposing a portion of the electrical interconnect structure. At least one semiconductor die can be bonded to the interposer and inside the aperture. Consequently, the height of the semiconductor package is lower than the design of disposing the semiconductor die on top of the interposer.

First claim

What is claimed is:

1. An interposer for a semiconductor package, comprising:
a substrate portion having a first side, a second side, and an electrical interconnect structure between the first side and the second side, wherein the substrate portion is substantially free from conductive through vias; and
a wall portion disposed on the first side and defining an aperture exposing a portion of the electrical interconnect structure,
wherein the wall portion comprises an intervening layer disposed on the substrate portion and a stiffener disposed on the intervening layer, the intervening layer and the stiffener having a same width.

2. The interposer for a semiconductor package of claim 1 , wherein the electrical interconnect structure comprises:
at least one first conductive terminal disposed on the first side;
at least one second conductive terminal disposed on the second side; and
at least one conductive line electrically connects the at least one first conductive terminal and the at least one second conductive terminal.

3. The interposer for a semiconductor package of claim 1 , wherein the substrate portion and the wall portion are formed of different materials.

4. The interposer for a semiconductor package of claim 1 , wherein the wall portion has a third side above the first side of the substrate portion, and the wall portion has at least one conductive through via penetrating through the wall portion.

5. The interposer for a semiconductor package of claim 4 , further comprising at least one third conductive terminal disposed on the third side, and the at least one conductive through via electrically connects the at least one third conductive terminal to the interconnect structure.

6. The interposer for a semiconductor package of claim 5 , comprising a plurality of third conductive terminals separated by dielectric material on top of the wall portion.

7. A semiconductor package, comprising:
an interposer comprising:
a substrate portion having a first side, a second side, and an electrical interconnect structure between the first side and the second side, wherein the substrate portion is substantially free from conductive through vias; and
a wall portion disposed on the first side and defining an aperture exposing a portion of the electrical interconnect structure; and
at least one first semiconductor die bonded to the interposer and disposed in the aperture,

wherein the wall portion comprises an intervening layer disposed on the substrate portion and a stiffener disposed on the intervening layer, the intervening layer and the stiffener having a same width.

8. The semiconductor package of claim 7 , wherein the electrical interconnect structure comprises:
at least one first conductive terminal disposed on the first side, wherein the at least one first semiconductor die is electrically connected to the at least one first conductive terminal;
at least one second conductive terminal disposed on the second side; and
at least one conductive line electrically connects the at least one first conductive terminal and the at least one second conductive terminal.

9. The semiconductor package of claim 7 , wherein the substrate portion and the wall portion are formed of different materials.

10. The semiconductor package of claim 7 , wherein the wall portion has a third side above the first side of the substrate portion, and the wall portion has at least one conductive through via penetrating through the wall portion.

11. The semiconductor package of claim 10 , further comprising at least one third conductive terminal disposed on the third side, and the at least one conductive through via electrically connects the at least one third conductive terminal to the interconnect structure.

12. The semiconductor package of claim 11 , comprising a plurality of third conductive terminals separated by dielectric material on top of the wall portion.

13. The semiconductor package of claim 11 , further comprising at least one second semiconductor die bonded to the at least one third conductive terminal, and the at least one second semiconductor die is disposed above the at least one first semiconductor die.

14. The semiconductor package of claim 7 , further comprising an object bonded to the second side of the interposer.

15. A method for preparing a semiconductor package, comprising the steps of:
providing an interposer comprising:
a substrate portion having a first side, a second side, and an electrical interconnect structure between the first side and the second side, wherein the substrate portion is substantially free from conductive through vias; and
a wall portion disposed on the first side and defining an aperture exposing the first side; and
bonding at least one first semiconductor die to the interposer and in the aperture,

wherein the wall portion comprises an intervening layer disposed on the substrate portion and a stiffener disposed on the intervening layer, the intervening layer and the stiffener having a same width.

16. The method for preparing a semiconductor package of claim 15 , wherein providing an interposer comprises:
forming the electrical interconnect structure on a first side of the substrate portion; and
performing an etching process from a second side of the substrate portion to form the wall portion defining the aperture exposing a portion of the electrical interconnect structure.

17. The method for preparing a semiconductor package of claim 15 , wherein providing an interposer comprises:
forming the electrical interconnect structure on a first side of the substrate portion;
thinning the substrate portion from a second side of the substrate portion to expose the electrical interconnect structure;
forming the intervening layer on the second side of the substrate portion; and
forming the wall portion on the intervening layer and defining the aperture.

18. The method for preparing a semiconductor package of claim 15 , wherein providing an interposer comprises forming at least one conductive through via penetrating through the wall portion.

19. The method for preparing a semiconductor package of claim 15 , wherein the wall portion has a third side above the first side of the substrate portion, the method further comprises forming at least one third conductive terminal on the third side, bonding at least one second semiconductor die to the at least one third conductive terminal, and the at least one second semiconductor die is disposed above the at least one first semiconductor die.

20. The method for preparing a semiconductor package of claim 15 , further comprising bonding an object to the interposer.

Assignees

• Nanya Technology Corp

Inventors

• Lin Po Chun

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title