Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9761531-B2
Application number	US-201514842545-A
Country	US
Kind code	B2
Filing date	Sep 1, 2015
Priority date	Mar 13, 2015
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

According to one embodiment, a semiconductor device is disclosed. The device includes interconnects each including a catalyst layer and a graphene layer thereon. The catalyst layer includes a first to fifth catalyst regions arranged along a first direction in order of the first to fifth catalyst regions. The first, third and fifth catalyst regions include upper surfaces higher than those of the second and fourth catalyst regions. Adjacent ones of the first to fifth catalyst regions are in contact with each other. A distance between the first and the third catalyst region and a distance between the third and fifth catalyst region are greater than a mean free path of graphene. The graphene layer includes a first graphene layer on the second catalyst region and a second graphene layer on the fourth catalyst region.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate; and
a first interconnect and a second interconnect provided on the substrate, each interconnect comprising a catalyst layer and first and second graphene layers provided on the catalyst layer,
the catalyst layer including a first catalyst region, a second catalyst region, a third catalyst region, a fourth catalyst region and a fifth catalyst region which are continuously arranged along a first direction in order of the first, second, third, fourth and fifth catalyst regions,
the first, third, and fifth catalyst regions comprising upper surfaces higher than upper surfaces of the second and fourth catalyst regions,
a distance between the first catalyst region and the third catalyst region, and a distance between the third catalyst region and fifth catalyst region being greater than or equal to 0.1 μm, and
the first graphene layer being provided on the second catalyst region, and the second graphene layer being provided on the fourth catalyst region,

wherein:
the catalyst layer of the second interconnect corresponds to the catalyst layer of the first interconnect,
the first and second graphene layers of the second interconnect correspond to the first and second graphene layers of the first interconnect, respectively, and
the first and second interconnects are arranged along a second direction different from the first direction.

2. The device according to claim 1 , wherein:
the first catalyst regions of the first and second interconnects are arranged along a first line parallel to the second direction,
the third catalyst regions of the first and second interconnects are arranged along a second line parallel to the second direction, and the second line is different from the first line, and
the fifth catalyst regions of the first and second interconnects are arranged along a third line parallel to the second direction, and the third line is different from the first and second lines.

3. The device according to claim 1 , wherein:
the first catalyst regions of the first and second interconnects are arranged along a first line non-parallel to the first and second directions,
the third catalyst regions of the first and second interconnects are arranged along a second line non-parallel to the first and second directions, and the second line is different from the first line, and
the fifth catalyst regions of the first and second interconnects are arranged along a third line non-parallel to the second direction, and the third line is different from the first and second lines.

4. The device according to claim 1 , wherein the first and second interconnects have a same thickness.

5. The device according to claim 1 , wherein the first and second interconnects each further includes a catalyst foundation layer provided under the catalyst layer.

6. The device according to claim 5 , wherein the catalyst foundation layer, the first catalyst region, the third catalyst region, the fifth catalyst region, the first graphene layer, and the second graphene layer have same lengths in a direction perpendicular to the first direction.

7. The device according to claim 1 , wherein the first, third and fifth catalyst regions are thicker than the second and fourth catalyst regions.

8. The device according to claim 1 , further comprising convex patterns provided under the first, third and fifth catalyst regions.

9. The device according to claim 1 , further comprising a plug connected to an upper surface of the first, third, or fifth catalyst region.

10. The device according to claim 9 , wherein a material of the plug includes refractory metal.

11. The device according to claim 1 , wherein the first and second interconnects are a plurality of bit lines.

12. The device according to claim 1 , wherein the first, third, and fifth catalyst regions include impurities.

13. The device according to claim 1 , wherein the first and second interconnects extend in the first direction.

14. The device according to claim 1 , further comprising an insulating film provided between the first and second interconnects.

Assignees

• Toshiba Kk

Inventors

• Saito Tatsuro
• Kitamura Masayuki
• Sakata Atsuko
• Wada Makoto
• Kajita Akihiro
• Sakai Tadashi

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title

• H10W20/052

  by treatments not introducing additional elements therein · CPC title

• H10W20/045

  for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD] · CPC title

• H10W20/4462 Primary

  Carbon or carbon-containing materials, e.g. graphene · CPC title