Shared control of a phase locked loop (PLL) for a multi-port physical layer (PHY)

Patent metadata

Field	Value
Publication number	US-9760515-B2
Application number	US-201514679436-A
Country	US
Kind code	B2
Filing date	Apr 6, 2015
Priority date	Apr 6, 2015
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

Methods and systems for shared control of a phase locked loop (PLL) for a multi-port physical layer (PHY) are disclosed. In one aspect, an arbitration logic circuit is coupled to ports of a multi-port PHY sharing a phase locked loop (PLL). Upon receiving an indication that the shared PLL is to be reset, the arbitration logic circuit commands the ports sharing the PLL to enter a state in which any reset of the shared PLL would have minimal or no effect in their operations. In this manner, an integrated circuit (IC) including a multi-port PHY may be configured with only one PLL and associated clock generating logic to provide a clock signal for some or all of its ports, thus reducing its semiconductor area and power consumption. Furthermore, the ports of the multi-port PHY may operate independently from each other obviating any configuration and/or interoperability problems associated with having a shared PLL.

First claim

What is claimed is:

1. A method for controlling a multi-port physical layer (PHY), comprising:
providing, by an arbitration logic circuit coupled to a plurality of port controllers of a multi-port PHY and to a phase locked loop (PLL) of the multi-port PHY, a command to enter a low power mode to a first port controller of the plurality of port controllers in response to a PLL reset request from a second port controller of the plurality of port controllers; and
providing, by the arbitration logic circuit, a PLL reset command to the PLL in response to an indication that the first port controller has entered the low power mode.

2. The method of claim 1 , wherein the first port controller is independent from the second port controller.

3. The method of claim 1 , wherein each port controller of the plurality of port controllers is independent from all other port controllers of the plurality of port controllers.

4. The method of claim 1 , wherein the first port controller and the second port controller are coupled to the PLL.

5. The method of claim 1 , wherein the plurality of port controllers are coupled to the PLL.

6. The method of claim 1 , wherein the first port controller and the second port controller correspond to distinct Peripheral Component Interface Express (PCIe) link lanes.

7. The method of claim 1 , further comprising:
providing, by the arbitration logic circuit, a command to exit the low power mode to the first port controller and to the second port controller in response to an indication that the PLL is reset.

8. The method of claim 1 , wherein the plurality of port controllers are coupled to the PLL to generate a corresponding plurality of clock signals and each port controller of the plurality of port controllers is independent from all other port controllers of the plurality of port controllers, the method further comprising:
providing, by the arbitration logic circuit, the command to enter the low power mode to the plurality of port controllers other than the first port controller, in response to the PLL reset request from the second port controller.

9. The method of claim 8 , further comprising providing, by the arbitration logic circuit, a command to exit the low power mode to the plurality of port controllers in response to an indication that the PLL is reset.

10. The method of claim 1 , further comprising providing, from the arbitration logic circuit to a port PHY, a PHY command to enter the low power mode.

11. The method of claim 1 , further comprising providing, from the arbitration logic circuit to a port PHY, a PHY command to exit the low power mode.

12. An integrated circuit (IC) comprising:
an arbitration logic circuit;
a phase locked loop (PLL) coupled to the arbitration logic circuit; and
a plurality of port controllers of a multi-port physical layer (PHY), wherein at least a first port controller and a second port controller of the plurality of port controllers are coupled to the PLL;
the arbitration logic circuit configured to:
provide a command to enter a low power mode to the first port controller in response to a PLL reset request from the second port controller; and
provide a PLL reset command to the PLL in response to an indication that the first port controller has entered the low power mode.

13. The IC of claim 12 , wherein the first port controller is configured to operate independently from the second port controller.

14. The IC of claim 12 , wherein the first port controller and the second port controller are coupled to the PLL.

15. The IC of claim 12 , wherein the first port controller and the second port controller are configured to operate as distinct Peripheral Component Interface Express (PCIe) link lanes.

16. The IC of claim 12 , wherein the arbitration logic circuit is further configured to provide a command to exit the low power mode to the first port controller and to the second port controller in response to an indication that the PLL is reset.

17. The IC of claim 12 , further comprising a first port PHY associated with a first one of the plurality of port controllers.

18. The IC of claim 17 , wherein the arbitration logic circuit is further configured to instruct the first port PHY to enter the low power mode.

19. The IC of claim 18 , wherein the arbitration logic circuit is further configured to instruct the first port PHY to exit the low power mode.

20. The IC of claim 12 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a computer; a portable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; and a portable digital video player.

21. An integrated circuit (IC) comprising:
a means for arbitrating a reset of a means for generating a clock signal, the means for generating the clock signal coupled to the means for arbitrating the reset; and
a plurality of means for controlling a port of a multi-port physical layer (PHY), wherein at least a first means for controlling a first port and a second means for controlling a second port of the plurality of means for controlling a port are coupled to the means for generating the clock signal;
the means for arbitrating the reset configured to:
provide a command to enter a low power mode to the first means for controlling the first port in response to a phase locked loop (PLL) reset request from the second means for controlling the second port; and
provide a PLL reset command to the means for generating the clock signal in response to an indication that the first means for controlling the first port has entered the low power mode.

22. The IC of claim 21 , wherein the first means for controlling the first port is configured to operate independently from the second means for controlling the second port.

23. The IC of claim 21 , wherein the first means for controlling the first port and the second means for controlling the second port are coupled to the PLL.

24. The IC of claim 21 , wherein the first means for controlling the first port and the second means for controlling the second port are configured to operate as distinct Peripheral Component Interface Express (PCIe) link lanes.

25. The IC of claim 21 , wherein the means for arbitrating the reset is further configured to provide a command to exit the low power mode to the first means for controlling the first port and the second means for controlling the second port in response to an indication that the PLL is reset.

Assignees

• Qualcomm Inc

Inventors

• Winemiller Chad Everett
• Barash Dror
• Deans Russell Coleman
• Vilas Mark Wesley

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/372 Primary

  using a time-dependent priority, e.g. individually loaded time counters or time slot · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/32 Primary

  Means for saving power · CPC title