Dynamically modifying a power/performance tradeoff based on a processor utilization

Patent metadata

Field	Value
Publication number	US-9760409-B2
Application number	US-201615162709-A
Country	US
Kind code	B2
Filing date	May 24, 2016
Priority date	Dec 15, 2011
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a plurality of cores;
at least one graphics engine;
a shared cache memory; and
a power controller, the power controller including a policy switching circuit to dynamically update a power management policy, the power management policy selectable by a user from a plurality of policies provided by an operating system including a power saver policy, a balanced policy and a performance policy, to the performance policy when a ratio of a duration of a maximum performance state residency of the processor during an evaluation interval to a duration of an active state residency of the processor during the evaluation interval exceeds a threshold level.

2. The processor of claim 1 , wherein the processor is to dynamically and automatically switch from a selected one of the plurality of policies to the performance policy when a utilization of the processor exceeds the threshold level.

3. The processor of claim 2 , wherein the processor is to dynamically and automatically switch from the performance policy to the selected one of the plurality of policies when the utilization is less than a second threshold level, the second threshold level less than the threshold level.

4. The processor of claim 1 , wherein the policy switching circuit includes a dynamic loadline tuning circuit comprising:
a maximum performance accumulator to accumulate the maximum performance state residency during the evaluation interval;
an active state accumulator to accumulate the active state residency during the evaluation interval; and
an accumulator sampler to sample the maximum performance accumulator and the active state accumulator.

5. The processor of claim 4 , wherein the dynamic loadline tuning circuit further comprises a comparator to compare the ratio to at least one of the threshold level and a second threshold level.

6. The processor of claim 5 , wherein the dynamic loadline tuning circuit is to update the power management policy to the performance policy when the ratio is greater than the threshold level.

7. The processor of claim 4 , further comprising a first active state mask to store a state of the plurality of cores at a first time period and a second active state mask to store a state of the plurality of cores at a second time period, and wherein the active state accumulator is to accumulate the active state residency based at least in part on the first and second active state masks and time stamps each associated with one of the plurality of cores and a current time stamp.

8. The processor of claim 1 , wherein the processor further comprises an integrated memory controller.

9. The processor of claim 1 , wherein the processor further comprises a display controller.

10. The processor of claim 1 , wherein the power saver policy includes a plurality of power oriented tunings for the processor.

11. The processor of claim 1 , further comprising a register to store an active one of the plurality of policies.

12. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
determining, in a circuit of a power controller of a multicore processor, an active state residency for a plurality of cores of the multicore processor during an evaluation interval;
determining, in the circuit, a maximum performance state residency for the plurality of cores during the evaluation interval;
determining, in the circuit, a ratio between the maximum performance state residency and the active state residency; and
setting a power management policy based at least in part on the ratio.

13. The non-transitory machine-readable medium of claim 12 , wherein the method further comprises if the ratio is greater than a high threshold, setting the power management policy to a performance policy.

14. The non-transitory machine-readable medium of claim 13 , wherein the method further comprises if the ratio is less than a low threshold, setting the power management policy to a power saver policy.

15. The non-transitory machine-readable medium of claim 14 , wherein the method further comprises if the ratio is between the high and low thresholds, maintaining a current power management policy.

16. The non-transitory machine-readable medium of claim 15 , wherein the method further comprises receiving the current power management policy from an operating system responsive to a user selection.

17. The non-transitory machine-readable medium of claim 14 , wherein the method further comprises dynamically updating the power management policy from the power saver policy to the performance policy when a utilization of the multicore processor exceeds a threshold.

18. A system comprising:
a multicore processor including a plurality of cores and a power controller including circuitry to dynamically switch a power management policy for the multicore processor from a power saver policy to a performance policy based at least in part on a first comparison between an active state residency for the multicore processor and a maximum performance state residency for the multicore processor and a second comparison between a result of the first comparison and a threshold level; and
a dynamic random access memory (DRAM) coupled to the multicore processor.

19. The system of claim 18 , wherein the power controller is to store a first active state mask to identify a state of the plurality of cores at a first time and a second active state mask to identify a state of the plurality of cores at a second time, and wherein the circuitry is to determine the active state residency based at least in part on the first and second active state masks, time stamps each associated with one of the plurality of cores and a current time stamp.

20. The system of claim 19 , wherein the power controller is to store a first performance state mask to identify a performance state of the plurality of cores at the first time and a second performance state mask to identify a performance state of the plurality of cores at the second time, and wherein the circuitry is to determine the maximum performance state residency based at least in part on the first and second performance state masks, the time stamps and the current time stamp.

Assignees

• Intel Corp

Inventors

• Sistla Krishnakanth V
• Rowland Mark
• Varma Ankush
• Steiner Ian M
• Bace Matthew
• Borkowski Daniel
• Garg Vivek
• Akturan Chelsea
• Ananthakrishnan Avinash N

Classifications

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• Y02B60/1217

  Cross-Sectional Technologies · mapped topic

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F9/5094 Primary

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title