Module board

US9756718B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9756718-B2
Application numberUS-201414160962-A
CountryUS
Kind codeB2
Filing dateJan 22, 2014
Priority dateJan 22, 2013
Publication dateSep 5, 2017
Grant dateSep 5, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A module board includes a base substrate. Electronic components are mounted on a first principal surface of the base substrate. The mounted electronic components are sealed by a sealing resin containing an SiO 2 filler. A top surface and side surfaces of the sealing resin are covered with a shield layer containing a carbon filler, which is flat powder, as a conductive component. A terminal electrode is formed on a second principal surface of the base substrate that is disposed opposite to the first principal surface of the base substrate.

First claim

Opening claim text (preview).

What is claimed is: 1. A module board comprising: a base substrate; first and second electronic components each mounted on one of principal surfaces of the base substrate; a sealing resin formed so as to seal the electronic component mounted on the one of the principal surfaces of the base substrate; a shield layer covering the sealing resin; and a shield section containing a metal and provided so as to contact with a portion of the shield layer, wherein the shield layer is a resin film containing carbon as a conductive component, wherein the shield section is provided between the sealing resin and the shield layer, and wherein the shield section is disposed only above the first electronic component, and does not extend to an area above the second electronic component. 2. The module board according to claim 1 , wherein the sealing resin contains an SiO 2 filler. 3. The module board according to claim 2 , wherein a coefficient of linear expansion of the shield layer is about 1 to 15 ppm/° C., and wherein a coefficient of linear expansion of the sealing resin is about 5 to 20 ppm/° C. 4. The module board according to claim 1 , wherein the carbon is flat powder. 5. The module board according to claim 2 , wherein the carbon is flat powder. 6. The module board according to claim 3 , wherein the carbon is flat powder.

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • batch processes · CPC title

  • H05K1/0218Primary

    by printed shielding conductors, ground planes or power plane (H05K1/0236 takes precedence) · CPC title

  • Electricity · mapped topic

  • Flakes, flat particles or lamellar particles · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9756718B2 cover?
A module board includes a base substrate. Electronic components are mounted on a first principal surface of the base substrate. The mounted electronic components are sealed by a sealing resin containing an SiO 2 filler. A top surface and side surfaces of the sealing resin are covered with a shield layer containing a carbon filler, which is flat powder, as a conductive component. A terminal ele…
Who is the assignee on this patent?
Murata Manufacturing Co
What technology area does this patent fall under?
Primary CPC classification H05K1/0218. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 05 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).