Electromagnetic interference shielding techniques

US9155188B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9155188-B2
Application numberUS-201213631156-A
CountryUS
Kind codeB2
Filing dateSep 28, 2012
Priority dateNov 4, 2011
Publication dateOct 6, 2015
Grant dateOct 6, 2015

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  1. Title

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  2. Abstract

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Methods and apparatuses are disclosed for fabricating a printed circuit board (PCB) having electromagnetic interference (EMI) shielding and also having reduced volume over conventional frame-and-shield approaches. Some embodiments include fabricating the PCB by mounting an integrated circuit to the PCB, outlining an area corresponding to the integrated circuit with a number of grounded vias, selectively applying an insulating layer over the PCB such that at least one of the grounded vias are exposed, and selectively applying a conductive layer over the PCB such that the conductive layer covers at least a portion of the integrated circuit and such that the conductive layer is coupled to the at least one of the grounded vias that are exposed.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus comprising: a circuit board comprising a first surface and a second surface; a first integrated circuit coupled to the first surface of the circuit board; a first pad on the first surface of the circuit board adjacent the first integrated circuit; a second pad on one of the first surface of the circuit board and the second surface of the circuit board; a conductive layer, wherein the conductive layer is electrically coupled to the first…

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What does patent US9155188B2 cover?
Methods and apparatuses are disclosed for fabricating a printed circuit board (PCB) having electromagnetic interference (EMI) shielding and also having reduced volume over conventional frame-and-shield approaches. Some embodiments include fabricating the PCB by mounting an integrated circuit to the PCB, outlining an area corresponding to the integrated circuit with a number of grounded vias, se…
Who is the assignee on this patent?
Apple Inc
What technology area does this patent fall under?
Primary CPC classification H05K1/0218. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).