Efficient peer-to-peer communication support in SoC fabrics

Patent metadata

Field	Value
Publication number	US-9755997-B2
Application number	US-201213810033-A
Country	US
Kind code	B2
Filing date	Jan 13, 2012
Priority date	Jan 13, 2012
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

Methods and apparatus for efficient peer-to-peer communication support in interconnect fabrics. Network interfaces associated with agents are implemented to facilitate peer-to-peer transactions between agents in a manner that ensures data accesses correspond to the most recent update for each agent. This is implemented, in part, via use of non-posted “dummy writes” that are sent from an agent when the destination between write transactions originating from the agent changes. The dummy writes ensure that data corresponding to previous writes reach their destination prior to subsequent write and read transactions, thus ordering the peer-to-peer transactions without requiring the use of a centralized transaction ordering entity.

First claim

What is claimed is:

1. A method for facilitating peer-to-peer write and read transactions between peer agents on a chip including an interconnect fabric, comprising:
implementing a plurality of network interfaces coupled to the interconnect fabric, each network interface associated with at least one peer agent and operatively coupled between the at least one agent and the interconnect fabric;
originating a plurality of write and read transactions at the peer agents; and
implementing logic in the plurality of network interfaces to order the peer-to-peer write and read transactions so as to ensure read transactions access most recent data.

2. The method of claim 1 , further comprising:
for a write transaction originating at an peer agent, storing a destination identifier (ID) corresponding to a destination of the write transaction in the network interface;
determining, in the network interface, if a destination ID corresponding to a current write transaction originating at the peer agent is different that a destination ID corresponding to an immediately preceding write transaction originating at the agent; and, if the two destination ID's are different,
sending out a dummy write from the peer agent onto the interconnect fabric to be routed to the previous destination prior to sending the current write transaction onto the interconnect fabric to be routed to its destination.

3. The method of claim 2 , wherein the dummy write comprises a non-posted write.

4. The method of claim 2 , further comprising waiting to receive an acknowledgement of the dummy write prior to sending the current write transaction to its destination.

5. The method of claim 2 , wherein a network interface stores the destination ID for the most recent write transactions for each peer agent associated with the network interface and generates dummy writes when sequential write transactions originating from the same peer agent have different destination IDs.

6. The method of claim 1 , wherein the plurality of network interfaces are implemented such that each network interface is associated with a respective peer agent.

7. The method of claim 2 , further comprising sending a write notification to at least one other peer agent indicating the destination corresponding to the current write transaction is available for data access.

8. The method of claim 1 , wherein the interconnect fabric comprises a two-dimensional mesh interconnect.

9. The method of claim 1 , wherein the peer agents and interconnect fabric are implemented on a System on a Chip (SoC).

10. An apparatus comprising:
an interconnect fabric;
a plurality of agents;
a plurality of processor cores, each coupled to a respective agent from among the plurality of agents;
a plurality of network interfaces, each operatively coupled between at least one agent and the interconnect fabric and including logic for facilitating peer-to-peer communication between the plurality of agents in a manner that ensures data transactions between peer agents are ordered such that data accessed by each data transaction comprises a most recent update of the data.

11. The apparatus of claim 10 , wherein the interconnect fabric comprises a Network on a Chip.

12. The apparatus of claim 10 , wherein a network interface comprises logic for facilitating operations comprising,
storing a destination identifier (ID) corresponding to a destination of first write transaction originating at an agent coupled to the network interface;
determining if a destination ID corresponding to a second write transaction originating at the agent coupled to the network interface is different that a destination ID corresponding to the first write transaction; and if the two destination ID's are different,
sending out a dummy write from the network interface onto the interconnect fabric to be routed to the destination for the first write transaction prior to sending the second write transaction onto the interconnect fabric to be routed to its destination.

13. The apparatus of claim 10 , wherein the apparatus comprises a System on a Chip (SoC).

14. The apparatus of claim 10 , wherein the apparatus includes a respective network interface coupled between each agent and the interconnect fabric.

15. The apparatus of claim 10 , wherein a network interface comprises:
an outbound queue;
an outbound arbiter;
a packetizer block;
a de-packetizer block;
an inbound queue;
an inbound arbiter;
and
a register, configured to store a destination identifier (ID) of a destination corresponding to a most recent write transaction.

16. A System on a Chip (SoC), comprising:
a plurality of Intellectual Property (IP) blocks, each having at least one peer agent and a network interface, at least a portion of the IP blocks further including a processor core separate from the at least one agent for the IP block;
an interconnect fabric, including a plurality of routers coupled to the plurality of IP blocks via the network interfaces;
wherein the network interfaces include logic for facilitating peer-to-peer communication between the agents in a manner that ensures data transactions between peer agents are ordered such that data accessed for each transaction comprises a most recent copy of the data.

17. The SoC of claim 16 , wherein the interconnect fabric comprises a two-dimensional mesh, a plurality of torus interconnects, or a three-dimensional interconnect.

18. The SoC of claim 16 , wherein the interconnect fabric and the plurality of routers comprise a Network on a Chip.

19. The SoC of claim 16 , wherein at least a portion of the IP blocks comprises processor core blocks including a processor core coupled to one or more levels of cache, and wherein an agent for the processor core blocks is employed for facilitating coherent memory transactions with other cache and memory agents in the SoC.

20. The SoC of claim 16 , wherein the network interfaces include logic for performing operations comprising:
storing a destination identifier (ID) corresponding to a destination of first write transaction originating at an agent coupled to the network interface;
determining if a destination ID corresponding to a second write transaction originating at the agent coupled to the network interface is different that a destination ID corresponding to the first write transaction; and if the two destination ID's are different,
sending out a dummy write from the network interface onto the interconnect fabric to be routed to the destination for the first write transaction prior to sending the second write transaction onto the interconnect fabric to be routed to its destination.

21. The method of claim 1 , wherein at least a portion of the agents is coupled to a processor core.

Assignees

• Li Bin
• Zhao Li
• Iyer Ravishankar
• Illikkal Rameshkumar G
• Intel Corp

Inventors

• Li Bin
• Zhao Li
• Iyer Ravishankar
• Illikkal Rameshkumar G

Classifications

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• H04L51/04 Primary

  Real-time or near real-time messaging, e.g. instant messaging [IM] · CPC title

• G06F2213/0038

  System on Chip · CPC title

• H04L49/109

  Integrated on microchip, e.g. switch-on-chip · CPC title

• H04L51/30

  Electricity · mapped topic