Pooled memory address translation

Patent metadata

Field	Value
Publication number	US-2016283399-A1
Application number	US-201514671566-A
Country	US
Kind code	A1
Filing date	Mar 27, 2015
Priority date	Mar 27, 2015
Publication date	Sep 29, 2016
Grant date	—

Abstract

A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The request includes a node address according to an address map of the computing node. An address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map and causes the particular shared memory controller to handle the request.

First claim

What is claimed is:

1 . An apparatus comprising:
a first shared memory controller comprising:
a first interface to receive, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool, wherein the request includes a node address according to an address map of the computing node;
translation logic to use an address translation structure to translate the first address into a corresponding second address according to a global address map for the memory pool;
routing logic to:
determine that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map; and
cause the particular shared memory controller to handle the request.

2 . The apparatus of claim 1 , wherein the particular shared memory controller is determined to be the first shared memory controller and the first shared memory controller is further to:
access the particular line of memory from a particular memory element included in a portion of the memory pool controlled by the first shared memory controller; and return a result to the computing node.

3 . The apparatus of claim 1 , wherein the plurality of shared memory controllers are to comprise a network of shared memory controllers and each one of the plurality of shared memory controllers is to control access to a respective portion of the memory pool.

4 . The apparatus of claim 1 , wherein the particular shared memory controller is determined to be a second shared memory controller and the first shared memory controller is to route the request to the second shared memory controller.

5 . The apparatus of claim 4 , wherein the first shared memory controller further comprises a second interface to forward the request to the second shared memory controller and receive a result for the request from the second shared memory controller, and the result is to be forwarded to the computing node over the first interface.

6 . The apparatus of claim 1 , wherein the particular shared memory controller is determined to be a second shared memory controller in the plurality of shared memory controller, the routing logic is further to determine a routing path to the second shared memory controller for the request, a third shared memory controller is included in the routing path, the first shared memory controller comprises a second interface and the request is to be sent to the third shared memory controller over the second interface to route the request to the second shared memory controller.

7 . The apparatus of claim 1 , wherein the address translation structure comprises a set of range registers.

8 . The apparatus of claim 1 , wherein the address translation structure comprises a table lookaside buffer (TLB).

9 . The apparatus of claim 8 , wherein the address translation structure further comprises a set of range registers.

10 . The apparatus of claim 9 , wherein a first portion of the node addresses of the address map of the computing node are to be translated using the set of range registers, and a second portion of the node addresses of the address map of the computing node are to be translated using the TLB.

11 . The apparatus of claim 9 , wherein the translation logic further comprises a TLB update handler to updates to the TLB.

12 . The apparatus of claim 1 , wherein the memory pool comprises system management memory, private memory, and shared memory.

13 . The apparatus of claim 1 , wherein the first interface uses a shared memory link protocol.

14 . The apparatus of claim 13 , wherein the shared memory link protocol utilizes physical layer logic of a different interconnect protocol.

15 . The apparatus of claim 14 , wherein the different interconnect protocol comprises a Peripheral Component Interconnect Express (PCIe)-based protocol.

16 . The apparatus of claim 13 , wherein the first shared memory controller further comprises a second interface to couple to another shared memory controller in the plurality of shared memory controllers.

17 . The apparatus of claim 16 , wherein the second interface uses an expanded version of the shared memory link protocol, and the expanded version of the shared memory link protocol enables routing of requests between shared memory controllers in the plurality of shared memory controllers.

18 . At least one machine accessible storage medium having code stored thereon, the code when executed on a machine, causes the machine to:
receive a flit corresponding to a request of memory by a computing node, wherein the request comprises a first address according to a memory map of the computing node, and the first address references a first line of the memory; translate the first address into a second address according to a global memory map of a system using an address translation structure; determine that a particular one of a plurality of shared memory controllers controls a portion of the memory corresponding to the second address; and route the request to the particular shared memory controller using the second address.

19 . A system comprising:
a memory comprising a plurality of memory elements; a shared memory controller to manage access to a subset of the plurality of memory elements; at least one computing node connected to the shared memory controller by a shared memory link, wherein the computing node is to:
generate a request relating to a particular line of the memory, wherein the request comprises a first address according to a memory map of the computing node, and the first address corresponds to the particular line of the memory; and
send the request to the shared memory controller;
wherein the shared memory controller comprises:
address translation logic to translate the first address into a corresponding second address according to a global address map of the memory using an address translation structure maintained at the shared memory controller; and
routing logic to determine which of a plurality of shared memory controllers is associated with the second address in the global address map.

20 . The system of claim 19 , wherein the system comprises the plurality of shared memory controllers and a plurality of computing nodes, wherein each shared memory controller is coupled to at least one respective computing node in the plurality of computing nodes.

Assignees

• Intel Corp

Inventors

• Das Sharma Debendra

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/404 Primary

  with address mapping · CPC title

• G06F12/1072

  Decentralised address translation, e.g. in distributed shared memory systems · CPC title

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title