ASAR ADC circuit and conversion method thereof

Patent metadata

Field	Value
Publication number	US-9755659-B2
Application number	US-201715407334-A
Country	US
Kind code	B2
Filing date	Jan 17, 2017
Priority date	Feb 3, 2016
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

The present disclosure provides asynchronous successive approximation register analog-to-digital converter (ASAR ADC) circuits and signal conversion method thereof. An exemplary ASAR AC circuit includes a sample/hold circuit configured to input a first analog signal and output a second analog signal; a digital-to-analog converter circuit configured to output a third analog signal; a first voltage comparison circuit configured to respond to a valid level of a latch signal, and output a first logic level and a second logic level; a first logic circuit configured to respond to a valid level of a flag signal, and identify a comparison result of the first voltage comparison circuit and output the first digit signal; and a pulse generation circuit configured to generate the latch signal and the flag signal with a generation time of the valid levels independently from the first logic level and the second logic level.

First claim

What is claimed is:

1. An asynchronous successive approximation register analog-to-digital converter (ASAR ADC) circuit, configured to covert a first analog signal into a first digital signal, the ASAR ADC circuit comprising:
a sample/hold circuit having an input terminal configured as an input terminal of the ASAR ADC to input the first analog signal, and an output terminal configured to output a second analog signal;
a digital-to-analog converter circuit having an input terminal configured to input the first digital signal, and an output terminal configured to output a third analog signal;
a first voltage comparison circuit, configured to respond to a valid level of a latch signal, and to compare the second analog signal with the third analog signal respectively inputted into a positive terminal of the first voltage comparison circuit and a negative terminal of the first voltage comparison circuit to output a first logic level and a second logic level;
a first logic circuit, configured to respond to a valid level of a flag signal, and to identify a comparison result of the first voltage comparison circuit according to the first logic level and the second logic level respectively inputted into the first logic circuit to output the first digit signal; and
a pulse generation circuit configured to generate the latch signal and the flag signal with a generation time of the valid levels of the latch signal and the flag signal independently from the first logic level and the second logic level.

2. The ASAR ADC circuit according to claim 1 , wherein the pulse generation circuit comprises;
a second voltage comparison circuit, responding to the latch signal, and configured to compare a fourth analog signal and a fifth analog signal respectively inputted into a positive input terminal and a negative input terminal of the second voltage comparison circuit to output a third logic level and a fourth logic level; and
a signal generation circuit configured to generate the latch signal and the flag signal.

3. The ASAR ADC circuit according to claim 2 , wherein:
the signal generation circuit is configured to identify the third logic level and the fourth logic level and determine if the second voltage comparison circuit finishes a comparison process;
the flag signal is turned into a valid level when the comparison process is completed;
the signal generation circuit is also configured to identify a comparison result when the second voltage comparison circuit finishes the comparison process;
a sum of time for the signal generation circuit to identify if the second voltage comparison circuit finishes the comparison and time for the signal generation circuit to identify the comparison result of the second voltage comparison circuit is referred to a first delay time;
a signal of the latch signal is a pulse signal; and
a pulse width of the latch signal is a sum of a preset second delay time and the first delay time.

4. The ASAR ADC circuit according to claim 3 , wherein:
a comparison delay of the second voltage comparison circuit is within a preset error range of a comparison delay of the first voltage comparison circuit under a same input signal.

5. The ASAR ADC circuit according to claim 4 , wherein:
the fourth analog signal and the fifth analog signal are big signals;
an amplitude of the fourth analog signal is equal to a voltage of a power source; and
an amplitude of the fifth analog signal is equal to one half of the voltage of the power source.

6. The method according to claim 3 , wherein the signal generation circuits comprises:
a comparison circuit status detection circuit configured to identify the third logic level and the fourth logic level to determine if the second voltage comparison circuit finishes a comparison process and turn the flag signal into a valid level if the comparison process is determined to be finished;
a second logic circuit configured to identify a comparison result of the second voltage comparison circuit when the second voltage comparison circuit finishes the comparison process, and output a first pulse signal when a process for identifying the comparison result is finished; and
a delay circuit configured to provide the preset second delay time to the first pulse signal, and output the latch signal.

7. The ASAR ADC circuit according to claim 6 , wherein:
the comparison circuit status detection circuit is an Exclusive-Or gate circuit; and
the flag signal outputted from the Exclusive-Or gate circuit is at a logic high level if the third logic level is opposite to the fourth logic high level.

8. The ASAR ADC circuit to claim 6 , wherein the delay circuit comprises:
at least one cascade-connected inverter.

9. The ASAR ADC circuit according to claim 1 , wherein the first voltage comparison circuit comprises:
a fully differential input/fully differential output comparison circuit.

10. The ASAR ADC circuit according to claim 9 , wherein:
an internal structure of the second voltage comparison circuit is identical to an internal structure of the first voltage comparison circuit.

11. The ASAR ADC circuit according to claim 6 , wherein:
an internal structure of the second logic circuit is identical to an internal structure of the first logic circuit.

12. A method for converting a analog signal to a digital signal using an asynchronous successive approximation register analog-to-digital converter (ASAR ADC) circuit having a sample/hold circuit, a digital-to-analog convertor circuit, a first voltage comparison circuit, a first logic circuit and a pulse generation circuit, the method comprising:
inputting a first analog signal into the sample/hold circuit and outputting a second analog signal;
inputting a first digital signal into the digital-to-analog converter circuit and outputting a third analog signal;
responding to a valid level of a latch signal, and comparing the second analog signal with the third analog signal using the first voltage comparison circuit for outputting a first logic level and a second logic level;
responding to a valid level of a flag signal, and identifying a comparison result of the first voltage comparison circuit according to the first logic level and the second logic level using the first logic circuit and outputting a first digital signal; and
generating the latch signal and the flag signal using the pulse generation circuit with a generation time of the valid levels of the latch signal and the flag signal being independent of the first logic level and the second logic level.

13. The method according to claim 12 , wherein:
the first analog signal is inputted in an input terminal of the sample/hold circuit;
the second analog signal is outputted from an output terminal of the sample/hold circuit;
the first digital signal is inputted in an input terminal of the digital-to-analog converter circuit;
the third analog signal is outputted from an output terminal of the digital-to-analog converter circuit;
the second analog signal is inputted in a positive terminal of the first voltage comparison circuit; and
the third analog signal is inputted in a negative terminal of the first voltage comparison circuit.

14. The method according to claim 12 , wherein the pulse generation circuit includes a second voltage comparison circuit and signal generation circuit, wherein:
the signal generation circuit is configured to generate the latch signal and the flag signal.

15. The method according to claim 14 , wherein:
a fourth analog signal and a fifth analog signal are inputted into a positive terminal and a negative terminal of the second voltage compa

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• XUN Ben Peng
• Liu Fei
• Guo meng meng
• Tang Hua
• Yang Haifeng

Classifications

• H03M1/125 Primary

  Asynchronous, i.e. free-running operation within each conversion cycle · CPC title

• H03M1/44

  Sequential comparisons in series-connected stages with change in value of analogue signal · CPC title

• H03M1/38 Primary

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/42

  Sequential comparisons in series-connected stages with no change in value of analogue signal · CPC title

• H03M1/46

  with digital/analogue converter for supplying reference values to converter · CPC title