Digitally tuned capacitors with tapered and reconfigurable quality factors

Patent metadata

Field	Value
Publication number	US-9293262-B2
Application number	US-201213586738-A
Country	US
Kind code	B2
Filing date	Aug 15, 2012
Priority date	Feb 28, 2008
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

The present disclosure describes tuning capacitors with tapered and reconfigurable quality factors. Digitally tuned capacitors (DTCs) that provide a variable quality factor (Q) while maintaining a constant or near constant capacitance as well as DTCs that provide one or more Q values in a tapered distribution while maintaining a constant or near constant capacitance are described. The present disclosure also describes DTCs that provide one or more capacitances in a tapered distribution and one or more Q values in a tapered distribution.

First claim

What is claimed is:

1. A digitally tuned capacitor (DTC) adapted for use in a circuit device, comprising:
a first terminal;
a second terminal; and
a plurality of bit stages in parallel between the first terminal and the second terminal, each bit stage comprising at least one switch connected with at least one capacitor,
wherein:
the plurality of bit stages is configured to be controlled by a numeric control word in binary representation, each bit of the numeric control word representing a switching state of one bit stage in the plurality of bit stages, wherein the switching state is either an ON state or an OFF state, and
states of the DTC with same number of ON states is configured to provide a variable quality factor while maintaining a constant or near constant capacitance around a fixed level.

2. The DTC according to claim 1 , wherein the DTC is configured to provide one or more quality factors in a tapered distribution and a constant capacitance in response to one or more switching states of the numeric control word, the one or more switching states having the same number of bits that represent ON states.

3. The DTC according to claim 1 , wherein the DTC is configured to provide one or more capacitances in a tapered distribution and one or more quality factors in a tapered distribution in response to one or more switching states of the numeric control word, the one or more switching states being binary coded.

4. The DTC according to claim 1 , wherein the DTC is configured to provide one or more capacitances in a tapered distribution and one or more quality factors in a tapered distribution in response to one or more switching states of the numeric control word, the one or more switching states being thermometer-coded.

5. The DTC according to claim 1 , wherein the DTC is configured to provide one or more capacitances in a tapered distribution and one or more quality factors in a tapered distribution, wherein higher capacitance values in the one or more capacitances are associated with lower quality factors in the one or more quality factors.

6. The DTC according to claim 1 , wherein the DTC is configured to provide one or more capacitances in a tapered distribution and one or more quality factors in a tapered distribution, wherein lower capacitance values in the one or more capacitances are associated with lower quality factors in the one or more quality factors.

7. The DTC according to claim 1 , wherein each bit stage is associated with a quality factor and number of switches in the at least one switch of each bit stage is a function of the quality factor.

8. The DTC according to claim 7 , wherein number of switches is lower in a bit stage that, when in an ON state, is associated with a higher quality factor than in a bit stage that, when in an ON state, is associated with a lower quality factor.

9. The DTC according to claim 1 , wherein:
the at least one switch in a particular bit stage, when in an ON state, is associated with an ON resistance; and
capacitance value of the at least one capacitor in the particular bit stage is a function of the ON resistance.

10. The DTC according to claim 1 , wherein:
the at least one switch in a particular bit stage, when in an ON state, is associated with an ON resistance; and
the ON resistance of the particular bit stage is a function of capacitance value of the at least one capacitor in the particular bit stage.

11. The DTC according to claim 1 , wherein:
the at least one switch in a particular bit stage, when in an ON state, is associated with an ON resistance; and
the ON resistance of the particular bit stage is a function of capacitance value of the at least one capacitor in one or more other bit stages among the plurality of bit stages.

12. The DTC according to claim 1 , wherein
the at least one switch in a particular bit stage, when in an ON state, is associated with an ON resistance; and
the ON resistance of the particular bit stage is a function of a difference between capacitance value of the at least one capacitor in the particular bit stage and the at least one capacitor in one or more other bit stages among the plurality of bit stages.

13. The DTC according to claim 1 , wherein equivalent capacitance of the at least one capacitor in one bit stage is equal to equivalent capacitance of the at least one capacitor in each remaining bit stage.

14. The DTC according to claim 1 , wherein each switch among the at least one switch in each bit stage is a microelectromechanical system switch, a diode, a diode connected bipolar junction transistor, a field effect transistor, or an accumulated charge control field effect transistor.

15. The DTC according to claim 1 , wherein each capacitor among the at least one capacitor in each bit stage is a fixed capacitor or a variable capacitor.

16. The DTC according to claim 15 , wherein a capacitor among the at least one capacitor in a particular bit stage is a variable capacitor, the variable capacitor comprising a varactor diode or a varactor dielectric.

17. A method of digitally tuning a tunable capacitor in a circuit device, comprising:
providing a first terminal;
providing a second terminal;
providing a plurality of bit stages connected in parallel between the first terminal and the second terminal, each bit stage comprising at least one switch connected with at least one capacitor;
applying a numeric control word in binary representation to the plurality of bit stages, each bit of the numeric control word representing a switching state of one bit stage in the plurality of bit stages, wherein the switching state is either an ON state or an OFF state;
selectively controlling capacitance between the first terminal and the second terminal based on switching states of each bit stage in the plurality of bit stages; and
configuring states of the tunable capacitor with same number of ON states to provide a variable quality factor while maintaining a constant or near constant capacitance around a fixed level.

18. The method according to claim 17 , wherein the numeric control word to be applied to the plurality of bit stages is based on quality factor to be provided by the tunable capacitor.

19. The method according to claim 17 , wherein the numeric control word to be applied to the plurality of bit stages is based on voltages to be applied to the first and/or second terminals.

20. The method according to claim 17 , wherein each switch among the at least one switch in each bit stage is a microelectromechanical system switch, a diode, a diode connected bipolar junction transistor, a field effect transistor, or an accumulated charge control field effect transistor.

21. The method according to claim 17 , wherein each capacitor among the at least one capacitor in each bit stage is a fixed capacitor or a variable capacitor.

22. The method according to claim 21 , wherein a capacitor among the at least one capacitor in a particular bit stage is a variable capacitor, the variable capacitor comprising a varactor diode or a varactor dielectric.

Assignees

• Bawell Shawn
• Broughton Robert
• Bacon Peter
• Greene Robert W
• Ranta Tero Tapio
• Peregrine Semiconductor Corp

Inventors

• Bawell Shawn
• Broughton Robert
• Bacon Peter
• Greene Robert W
• Ranta Tero Tapio

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H01F21/12

  discontinuously variable, e.g. tapped · CPC title

• H01G7/00 Primary

  Capacitors in which the capacitance is varied by non-mechanical means; Processes of their manufacture · CPC title

• H03M1/1061

  using digitally programmable trimming circuits · CPC title

• H03K17/102

  in field-effect transistor switches · CPC title