Peeling method and method of manufacturing semiconductor device

US9755148B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9755148-B2
Application numberUS-201615059623-A
CountryUS
Kind codeB2
Filing dateMar 3, 2016
Priority dateAug 22, 2001
Publication dateSep 5, 2017
Grant dateSep 5, 2017

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

There is provided a peeling method capable of preventing a damage to a layer to be peeled. Thus, not only a layer to be peeled having a small area but also a layer to be peeled having a large area can be peeled over the entire surface at a high yield. Processing for partially reducing contact property between a first material layer ( 11 ) and a second material layer ( 12 ) (laser light irradiation, pressure application, or the like) is performed before peeling, and then peeling is conducted by physical means. Therefore, sufficient separation can be easily conducted in an inner portion of the second material layer ( 12 ) or an interface thereof.

First claim

Opening claim text (preview).

What is claimed is: 1. A display device comprising: a film comprising an organic material; a first insulating film on and in contact with the film; a thin film transistor over the first insulating film; a second insulating film over the thin film transistor; a pixel electrode over the second insulating film, the pixel electrode being electrically connected to the thin film transistor; a bank over an edge portion of the pixel electrode; a light emitting layer comprising an organic light emitting material over the pixel electrode; a second electrode over the light emitting layer; a protective film over the second electrode, wherein the protective film extends beyond a side edge of the bank and is in contact with a surface of the first insulating film. 2. The display device according to claim 1 , wherein the first insulating film comprises silicon and oxygen. 3. The display device according to claim 1 , wherein a channel forming region of the thin film transistor comprises silicon. 4. The display device according to claim 1 , further comprising a flexible substrate over the protective film. 5. The display device according to claim 1 , wherein the pixel electrode is an anode. 6. A display device comprising: a film comprising an organic material; a first insulating film on and in contact with the film; a thin film transistor over the first insulating film; a second insulating film over the thin film transistor; a pixel electrode over the second insulating film, the pixel electrode being electrically connected to the thin film transistor; a bank over an edge portion of the pixel electrode; a light emitting layer comprising an organic light emitting material over the pixel electrode; a second electrode over the light emitting layer; an organic resin film over the second electrode, wherein the organic resin film extends beyond a side edge of the bank and is in contact with a surface of the first insulating film. 7. The display device according to claim 6 , wherein the first insulating film comprises silicon and oxygen. 8. The display device according to claim 6 , wherein a channel forming region of the thin film transistor comprises silicon. 9. The display device according to claim 6 , further comprising a flexible substrate over the organic resin film. 10. The display device according to claim 6 , wherein the pixel electrode is an anode. 11. A display device comprising: a first flexible substrate; a first bonding layer on and in contact with the first flexible substrate; a first film comprising an organic material, the first film on and in contact with the first bonding layer; a first insulating film on and in contact with the first film; a thin film transistor over the first insulating film, the thin film transistor including a semiconductor film and a gate electrode with a gate insulating film interposed therebetween; a second insulating film over the thin film transistor; a pixel electrode over the second insulating film, the pixel electrode being electrically connected to the thin film transistor; a bank over an edge portion of the pixel electrode; a light emitting layer comprising an organic light emitting material over the pixel electrode; a second electrode over the light emitting layer; a third insulating film over the second electrode; a second bonding layer over the third insulating film; and a second film comprising an organic material, the second film on and in contact with the second bonding layer. 12. The display device according to claim 11 , wherein the first insulating film comprises silicon and oxygen. 13. The display device according to claim 11 , wherein the first bonding layer comprises a resin. 14. The display device according to claim 11 , wherein the first flexible substrate comprises a plastic. 15. The display device according to claim 11 , wherein the second film comprises a plastic. 16. An electronic apparatus comprising: a main body; and a display device supported by the main body, the display device comprising: a first flexible substrate; a first bonding layer on and in contact with the first flexible substrate; a first film comprising an organic material, the first film on and in contact with the first bonding layer; a first insulating film on and in contact with the first film; a thin film transistor over the first insulating film, the thin film transistor including a semiconductor film and a gate electrode with a gate insulating film interposed therebetween; a second insulating film over the thin film transistor; a pixel electrode over the second insulating film, the pixel electrode being electrically connected to the thin film transistor; a bank over an edge portion of the pixel electrode; a light emitting layer comprising an organic light emitting material over the pixel electrode; a second electrode over the light emitting layer; a third insulating film over the second electrode; a second bonding layer over the third insulating film; and a second film comprising an organic material, the second film on and in contact with the second bonding layer. 17. The display device according to claim 16 , wherein the first insulating film comprises silicon and oxygen. 18. The display device according to claim 16 , wherein the first bonding layer comprises a resin. 19. The display device according to claim 16 , wherein the first flexible substrate comprises a plastic. 20. The display device according to claim 16 , wherein the second film comprises a plastic.

Assignees

Inventors

Classifications

  • within silicon bodies · CPC title

  • Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

  • using bonding · CPC title

  • Thinning or removal of substrate · CPC title

  • PCBs, i.e. printed circuit boards · CPC title

Patent family

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Frequently asked questions

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What does patent US9755148B2 cover?
There is provided a peeling method capable of preventing a damage to a layer to be peeled. Thus, not only a layer to be peeled having a small area but also a layer to be peeled having a large area can be peeled over the entire surface at a high yield. Processing for partially reducing contact property between a first material layer ( 11 ) and a second material layer ( 12 ) (laser light irradiat…
Who is the assignee on this patent?
Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification H01L51/003. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 05 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).