Semiconductor devices including insulating gates and methods for fabricating the same

Patent metadata

Field	Value
Publication number	US-9755079-B2
Application number	US-201615000495-A
Country	US
Kind code	B2
Filing date	Jan 19, 2016
Priority date	Feb 23, 2015
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

Semiconductor devices are provided including a first active fin extending in a first direction and a second active fin spaced apart from the first active fin in a second direction perpendicular to the first direction, the second active fin extending in the first direction, the second active fin having a longer side shorter than a length of a longer side of the first active fin. A first dummy gate extends in the second direction overlapping a first end of each of the first and second active fins. A first metal gate extends in the second direction intersecting the first active fin and overlapping a second end of the second active fin. A first insulating gate extends in the second direction intersecting the first active fin. The first insulating gate extends into the first active fin.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first active fin extending in a first direction;
a second active fin, spaced apart from the first active fin in a second direction perpendicular to the first direction, the second active fin extending in the first direction and having a longer side that is shorter than a length of a longer side of the first active fin, wherein the first and second active fins overlap in the second direction;
a first dummy gate extending in the second direction overlapping with a first end of each of the first and second active fins;
a first metal gate extending in the second direction intersecting the first active fin and overlapping with a second end of the second active fin; and
a first insulating gate extending in the second direction intersecting the first and second active fins, respectively,
wherein the first insulating gate extends into the first active fin;
a third active fin spaced apart from the first active fin the first direction, the third active fin extending in the first direction;
a second dummy gate extending in the second direction overlapping the second end of the first active fin; and
a third dummy gate extending in the second direction overlapping the first end of the third active fin.

2. The semiconductor device of claim 1 , wherein a first pitch between the first insulating gate and the first metal gate and a second pitch between the first metal gate and the first dummy gate are different.

3. The semiconductor device of claim 2 , wherein the second pitch is larger than the first pitch.

4. The semiconductor device of claim 1 , wherein the first insulating gate intersects the second active fin.

5. The semiconductor device of claim 1 , further comprising:
a fourth active fin spaced apart from the second active fin in the first direction, the fourth active fin extending in the first direction, the fourth active fin having a longer side that is shorter than a length of a longer side of the third active fin; and
a second metal gate extending in the second direction to intersect the third active fin and overlapping the first end of the fourth active fin.

6. The semiconductor device of claim 5 , further comprising a second insulating gate extending in the second direction intersecting the third and fourth active fins.

7. A semiconductor device comprising:
a first active fin extending in a first direction;
a second active fin spaced apart from the first active fin in the first direction, the second active fin extending in the first direction;
a third active fin spaced apart from the first active fin in a second direction, the third active fin extending in the first direction;
a first dummy gate extending in the second direction perpendicular to the first direction overlapping with a first end of the first active fin, wherein the first dummy gate does not overlap with the third active fin;
a second dummy gate extending in the second direction overlapping a second end of the second active fin facing the first end of the first active fin;
a first normal gate extending in the second direction intersecting the first active fin;
a first insulating gate extending in the second direction intersecting the first and third active fins, respectively;
a second normal gate extending in the second direction intersecting the second active fin; and
a second insulating gate extending in the second direction intersecting the second active fin,
wherein the first insulating gate extends into the first active fin, and the second insulating gate extends into the second active fin, wherein the first and third active fins overlap in the second direction.

8. The semiconductor device of claim 7 ,
wherein either the first normal gate or the first insulating gate overlaps the first end of the third active fin; and
wherein the first dummy gate does not overlap the third active fin.

Assignees

• Park Sang-Jine
• Bai Keun-Hee
• Yeo Kyoung-Hwan
• Yoon Bo-Un
• Kwon Kee-Sang
• Kim Do-Hyoung
• Jeon Ha-Young
• Ha Seung-Seok
• Samsung Electronics Co Ltd

Inventors

• Park Sang-Jine
• Bai Keun-Hee
• Yeo Kyoung-Hwan
• Yoon Bo-Un
• Kwon Kee-Sang
• Kim Do-Hyoung
• Jeon Ha-Young
• Ha Seung-Seok

Classifications

• H01L29/495

  Electricity · mapped topic

• H01L27/0924

  Electricity · mapped topic

• H01L27/1211

  Electricity · mapped topic

• H01L27/0886

  Electricity · mapped topic

• H01L29/0657

  Electricity · mapped topic