Semiconductor device with U-shaped active portion

Patent metadata

Field	Value
Publication number	US-9754978-B2
Application number	US-201415028238-A
Country	US
Kind code	B2
Filing date	Sep 2, 2014
Priority date	Oct 11, 2013
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A semiconductor device ( 1001 ) includes: a first transistor ( 10 A) having a first channel length L 1 and a first channel width W 1 ; and a second transistor ( 10 B) having a second channel length L 2 and a second channel width W 2 , wherein the first transistor ( 10 A) and the second transistor ( 10 B) include an active layer formed from a common oxide semiconductor film, the first transistor ( 10 A) is a memory transistor which is capable of being irreversibly changed from a semiconductor state where a drain current Isd depends on a gate voltage Vg to a resistor state where the drain current Isd does not depend on the gate voltage Vg, and the first channel length L 1 is smaller than the second channel length L 2.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a substrate;
a first transistor supported on the substrate, the first transistor having a first channel length L 1 and a first channel width W 1 ; and
a second transistor supported on the substrate, the second transistor having a second channel length L 2 and a second channel width W 2 , wherein
the first transistor and the second transistor include an active layer made of a common oxide semiconductor film,
the first transistor is a memory transistor which is capable of being irreversibly changed from a semiconductor state where a drain current lsd depends on a gate voltage Vg to a resistor state where the drain current lsd does not depend on the gate voltage Vg, and
the first channel length L 1 is smaller than the second channel length L 2 ,
each of the first transistor and the second transistor includes:
a gate electrode,
a gate insulating film covering the gate electrode,
an active layer on the gate insulating film,
a source electrode on the active layer and in contact with a portion of the active layer, and
a drain electrode on the active layer and in contact with another portion of the active layer,

in the first transistor, when viewed in a direction normal to the substrate, a first portion of the active layer which extends over the gate electrode with the gate insulating film interposed therebetween and which is between the source electrode and the drain electrode has a U-shape, and
in the second transistor, when viewed in the direction normal to the substrate, a second portion of the active layer which extends over the gate electrode with the gate insulating film interposed therebetween and which is between the source electrode and the drain electrode has a rectangular shape.

2. The semiconductor device of claim 1 , wherein a ratio L 1 /W 1 of the channel length to the channel width in the first transistor, is smaller than a ratio L 2 /W 2 of the channel length to the channel width in the second transistor.

3. The semiconductor device of claim 1 , further comprising a memory circuit which includes the first transistor, wherein the second transistor includes a transistor which is a constituent of the memory circuit.

4. The semiconductor device of claim 3 , wherein
the memory circuit includes a plurality of memory cells,
each of the plurality of memory cells includes the first transistor and at least one select transistor for memory cell selection,
the at least one select transistor is the second transistor, and
the first transistor and the second transistor are connected in series.

5. The semiconductor device of claim 4 , wherein the at least one select transistor includes two or more select transistors that are connected in parallel.

6. The semiconductor device of claim 1 , wherein
the substrate includes a power supply domain region which includes the first transistor, and
the second transistor includes a transistor which is a constituent of a circuit provided in the power supply domain region.

7. The semiconductor device of claim 6 , wherein the channel length L 1 of the first transistor is not more than a smallest value of channel lengths of all transistors provided in the power supply domain region, each of which includes an active layer made of the common oxide semiconductor film.

8. The semiconductor device of claim 1 , wherein
the semiconductor device is an active matrix substrate, the active matrix substrate including
a display region which includes a plurality of pixel electrodes and switching elements each electrically connected with a corresponding one of the plurality of pixel electrodes, and
a peripheral region provided in a region other than the display region, the peripheral region including a plurality of circuits, and
the second transistor includes at least one of a plurality of transistors which are constituents of the plurality of circuits in the peripheral region.

9. The semiconductor device of claim 8 , wherein the channel length L 1 of the first transistor is not more than a smallest value of channel lengths of all transistors provided in the peripheral region, each of which has an active layer made of the common oxide semiconductor film.

10. The semiconductor device of claim 8 , wherein the second transistor includes a transistor which functions as the switching element.

11. The semiconductor device of claim 1 , wherein a ratio L 1 /W 1 of the channel length to the channel width in the first transistor, is not more than a smallest value of ratios of a channel length to a channel width in all transistors which have an active layer made of the common oxide semiconductor film.

12. The semiconductor device of claim 1 , wherein the common oxide semiconductor film is an In—Ga—Zn—O based semiconductor film.

13. The semiconductor device of claim 12 , wherein the In—Ga—Zn—O based semiconductor film includes a crystalline portion.

14. The semiconductor device of claim 1 , wherein
when the first transistor is in the semiconductor state, while an absolute value of a voltage between the source electrode and the drain electrode is in a range of not less than 0.1 V and not more than 10 V, there is a voltage range for the gate voltage in which an absolute value of a drain current per unit channel width, Ids/W 1 , falls in an electric current state of not more than 1×10 −14 A/μm, and
after transition to the resistor state, even when the gate voltage is set within the voltage range while the absolute value of the voltage between the source electrode and the drain electrode is in a range of not less than 0.1 V and not more than 10 V, an absolute value of a drain current per unit channel width, Ids/W 1 , falls in an electric current state of not less than 1×10 −11 A/μm according to the voltage between the source electrode and the drain electrode.

15. The semiconductor device of claim 1 , wherein the first transistor and the second transistor are thin film transistors.

16. The semiconductor device of claim 1 , wherein the first transistor and the second transistor are connected in series.

17. The semiconductor device of claim 1 , wherein the first transistor further includes an upper gate electrode above the active layer with an interlayer insulating layer interposed therebetween, the upper gate electrode arranged to overlap at least the first portion of the active layer when viewed in the direction normal to the substrate.

18. A semiconductor device, comprising:
a substrate;
a first transistor supported on the substrate, the first transistor having a first channel length L 1 and a first channel width W 1 ; and
a second transistor supported on the substrate, the second transistor having a second channel length L 2 and a second channel width W 2 , wherein
the first transistor and the second transistor include an active layer made of a common oxide semiconductor film,
the first transistor is a memory transistor which is capable of being irreversibly changed to a resistor state where a drain current lsd does not depend on a gate voltage Vg, and
the first channel width W 1 is greater than the second channel width W 2 and L 1 <L 2 ,
each of the first transistor and the second transistor includes:
a gate electrode,
a gate insulating film covering the gate electrode,
an active layer on the gate insulating film,
a source electrode on the active layer and in contact with a portion of the active layer, and
a drain electrode on the active layer and in contact with another portion of the active layer,

in the first transistor, whe

Assignees

• Sharp Kk

Inventors

• Ueda Naoki
• Katoh Sumio

Classifications

• H01L27/115

  Electricity · mapped topic

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• H01L27/11206

  Electricity · mapped topic

• H01L27/1251

  Electricity · mapped topic

• H01L27/1255 Primary

  Electricity · mapped topic