Semiconductor device

Patent metadata

Field	Value
Publication number	US-9502133-B2
Application number	US-201415028240-A
Country	US
Kind code	B2
Filing date	Sep 2, 2014
Priority date	Oct 11, 2013
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A memory cell ( 101 ) includes a memory transistor ( 10 A) having channel length L 1 and channel width W 1 , and a plurality of select transistors ( 10 B) each electrically being connected in series with the memory transistor and independently having channel length L 2 and channel width W 2 , wherein each of the memory transistor and the plurality of select transistors includes an active layer ( 7 A) formed from a common oxide semiconductor film, the memory transistor is a transistor which is capable of being irreversibly changed from a semiconductor state where drain current Ids depends on gate voltage Vg to a resistor state where drain current Ids does not depend on gate voltage Vg, and channel length L 2 is greater than channel length L 1.

First claim

The invention claimed is:

1. A semiconductor device comprising at least one memory cell, the at least one memory cell including
a memory transistor having a first channel length L 1 and a first channel width W 1 , and
a plurality of select transistors, each of the plurality of select transistors electrically being connected in series with the memory transistor and independently having a second channel length L 2 and a second channel width W 2 ,
wherein each of the memory transistor and the plurality of selection transistors includes an active layer formed from a common oxide semiconductor film,
the memory transistor is a transistor which is capable of being irreversibly changed from a semiconductor state where a drain current Ids depends on a gate voltage Vg to a resistor state where the drain current Ids does not depend on the gate voltage Vg, and
the second channel length L 2 is greater than the first channel length L 1 .

2. The semiconductor device of claim 1 , wherein the plurality of select transistors are electrically connected in parallel with each other and share an identical gate control line.

3. The semiconductor device of claim 2 , wherein the second channel width W 2 is smaller than the first channel width W 1 .

4. The semiconductor device of claim 2 , wherein a ratio W 2 /L 2 of the second channel width W 2 to the second channel length L 2 in the plurality of select transistors is smaller than a ratio W 1 /L 1 of the first channel width W 1 to the first channel length L 1 in the memory transistor.

5. The semiconductor device of claim 2 , wherein a sum of the second channel widths W 2 of the plurality of select transistors is greater than the first channel width W 1 of the memory transistor.

6. The semiconductor device of claim 1 , wherein
the memory transistor is supported by a substrate,
the memory transistor includes
a gate electrode,
a gate insulating film covering the gate electrode,
the active layer provided on the gate insulating film,
a source electrode provided on the active layer so as to be in contact with a part of the active layer, and
a drain electrode provided on the active layer so as to be in contact with another part of the active layer, and

when viewed in a direction normal to the substrate, a portion of the active layer which extends over the gate electrode with the gate insulating film interposed therebetween and which is located between the source electrode and the drain electrode has a U-shape.

7. The semiconductor device of claim 1 , wherein the oxide semiconductor film is an In—Ga—Zn—O based semiconductor film.

8. The semiconductor device of claim 7 , wherein the In—Ga—Zn—O based semiconductor film includes a crystalline portion.

9. The semiconductor device of claim 1 , wherein the memory transistor and the plurality of select transistors are thin film transistors.

10. The semiconductor device of claim 1 , wherein the memory transistor is either of a memory transistor S which is in the semiconductor state or a memory transistor R which is in the resistor state.

11. The semiconductor device of claim 10 , wherein
the at least one memory cell is a plurality of memory cells,
in some of the plurality of memory cells, the memory transistor is the memory transistor S, and
in other ones of the plurality of memory cells, the memory transistor is the memory transistor R.

12. The semiconductor device of claim 10 , wherein
in the memory transistor S, while an absolute value of a drain-source voltage is in a range of not less than 0.1 V and not more than 10 V, there is a voltage range for the gate-source voltage in which an absolute value of the drain current Ids divided by the channel width W 1 , Ids/W 1 , is not more than 1×10 −14 A/μm, and
in the memory transistor R, even when the gate-source voltage is set within the voltage range while the absolute value of the drain-source voltage is in a range of not less than 0.1 V and not more than 10 V, the absolute value of the drain current Ids divided by the channel width W 1 , Ids/W 1 , varies depending on the drain-source voltage so as to be not less than 1×10 −11 A/μm.

13. The semiconductor device of claim 10 , wherein
the at least one memory cell is a single memory cell and includes the memory transistor S,
an internal node is formed by connection of the memory transistor S and the plurality of select transistors, and
while the memory transistor S is in an ON state, a low-level voltage VL is output from the internal node when a gate voltage of the plurality of select transistors is a high-level voltage VH, and a high-level voltage VH is output from the internal node when the gate voltage of the plurality of select transistors is a low-level voltage VL.

14. The semiconductor device of claim 10 , wherein
the at least one memory cell is a single memory cell and includes either of the memory transistor S or the memory transistor R,
an internal node is formed by connection of either of the memory transistor S or the memory transistor R and the plurality of select transistors,
when the at least one memory cell includes the memory transistor S, a gate voltage of the memory transistor S is set to a low-level voltage VL that prevents the memory transistor S from transitioning to an ON state, and a gate voltage of the plurality of select transistors is set to a high-level voltage VH, a low-level voltage VL is output from the internal node, and
when the at least one memory cell includes the memory transistor R, a gate voltage of the memory transistor R is set to a low-level voltage VL that prevents the memory transistor R from transitioning to an ON state, and a gate voltage of the plurality of select transistors is set to a high-level voltage VH, a high-level voltage VH is output from the internal node.

15. The semiconductor device of claim 11 , further comprising:
a word line control circuit which controlls a plurality of first word lines and a plurality of second word lines;
a bit line control circuit which controlls a plurality of bit lines; and
a sense amplifier circuit which detects a reading signal from the plurality of memory cells,
wherein the plurality of memory cells are arranged in a row direction and a column direction,
gate electrodes of the memory transistors included in memory cells arranged in the same row are connected with the word line control circuit via one of the plurality of first word lines corresponding to that row,
a gate electrode of each of the plurality of select transistors included in memory cells arranged in the same row is connected with the word line control circuit via one of the plurality of second word lines corresponding to that row, and
drain electrodes of the memory transistors included in memory cells arranged in the same column are connected with the bit line control circuit and the sense amplifier circuit via one of the plurality of bit lines corresponding to that column.

16. The semiconductor device of claim 11 , further comprising:
a word line control circuit which controlls first and second word lines;
a bit line control circuit which controlls a plurality of bit lines; and
a sense amplifier circuit which detects a reading signal from the plurality of memory cells,
wherein the plurality of memory cells are arranged in a row direction,
gate electrodes of the memory transistors included in the plurality of memory cells are connected with the word line control circuit via the first word line,
a gate electrode of each of the plurality of select transistors included in the plurality of memory cells is connected with the word l

Assignees

• Sharp Kk

Inventors

• Ueda Naoki
• Katoh Sumio

Classifications

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title

• H10D62/235

  of IGFETs (IGFETs having buried channels H10D30/637) · CPC title

• H10D62/80

  characterised by the materials · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H01L29/24

  Electricity · mapped topic