Stacked semiconductor apparatus, system and method of fabrication

Patent metadata

Field	Value
Publication number	US-9754921-B2
Application number	US-201514683195-A
Country	US
Kind code	B2
Filing date	Apr 10, 2015
Priority date	Jan 15, 2008
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.

First claim

What is claimed is:

1. Electronics comprising:
a plurality of semiconductor devices stacked vertically one atop the other,
each of the semiconductor devices comprising a substrate having a front-side and a back-side, a circuit configured by circuit components, and an electrically conductive pattern including a first inter-device connection element disposed on the front-side of the substrate, a first back-side connection element disposed on the back-side of the substrate, and a first vertical connection element extending through the substrate,
the first inter-device connection element and the first vertical connection element each being electrically conductively connected to the circuit, and the first back-side connection element being electrically conductively connected to the first vertical connection element such that the circuit is electrically conductively connected to the back-side connection element via the first vertical connection element, and
wherein the electrically conductive patterns of the semiconductor devices are substantially the same,
for each lower one of the semiconductor devices and an upper one of the devices stacked directly thereon, the first inter-device connection element of the lower semiconductor device is electrically conductively connected to the first back-side connection element of the upper semiconductor device,
the circuits of the lower and upper semiconductor devices are electrically connected in series along a first conductive path that extends serially from the first vertical connection element of the lower semiconductor device to one point along the circuit of the lower semiconductor device, then from another point along the circuit of the lower semiconductor device to the first inter-device connection element of the lower semiconductor device, then from the first inter-device connection element of the lower semiconductor device to the first back-side connection element of the upper semiconductor device, then from the first back-side connection element of the upper semiconductor device to the first vertical connection element of the upper semiconductor device, and then from the first vertical connection element of the upper semiconductor device to one point along the circuit of the upper semiconductor device, and
the vertical connection elements of the semiconductor devices are centrally aligned with one another along a first vertical line, and the back-side connection elements of the semiconductor devices are centrally aligned with one another along a second vertical line that is spaced from the first vertical line.

2. The electronics of claim 1 , wherein the first inter-device connection elements of the semiconductor devices are centrally aligned with one another along a third vertical line spaced from the second vertical line.

3. The electronics of claim 2 , wherein the first vertical line that passes through the back-side connection elements of the semiconductor devices.

4. The electronics of claim 1 , wherein each of the semiconductor devices is a semiconductor memory device.

5. The electronics of claim 1 , wherein the conductive pattern of each of the semiconductor devices further includes a distribution line running along the front-side of the substrate of the semiconductor device from the vertical connection element of the semiconductor device and electrically conductively connected to the circuit of the device.

6. The apparatus of claim 1 , wherein the first inter-device connection element of each of the semiconductor devices is a metal bump.

7. The apparatus of claim 6 , wherein for each lower one of the semiconductor devices and an upper one of the devices stacked directly thereon, the metal bump of the lower semiconductor device and the back-side connection element of the upper device are joined directly to one another to physically connect the upper and lower semiconductor packages to one another.

8. An apparatus, comprising:
a stacked plurality of semiconductor devices, each of the semiconductor devices comprising a first connection path and a second connection path,
the first connection path comprising:
a first back-side connection element disposed on a back-side of a substrate,
a first inter-device connection element disposed on a front side of the substrate, and
a first vertical connection element connecting the first back-side connection element to the first inter-device connection element and extending through the substrate,
wherein the first back-side connection element, the first inter-device connection element, and the first vertical connection element are vertically aligned with one another, and
the second connection path comprising:
a second back-side connection element disposed on the back-side of the substrate,
a second inter-device connection element disposed on the front side of the substrate, and
a second vertical connection element connecting to the second inter-device connection element and extending through the substrate,

wherein the second inter-device connection element and the second vertical connection element are not vertically aligned with each other.

Assignees

• Park Ki-Tae
• Lee Kang-Wook
• Choi Young-Don
• Lee Yun-Sang
• Samsung Electronics Co Ltd

Inventors

• Park Ki-Tae
• Lee Kang-Wook
• Choi Young-Don
• Lee Yun-Sang

Classifications

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title