Designed-based interconnect structure in semiconductor structure
US-9281273-B1 · Mar 8, 2016 · US
Designed-based interconnect structure in semiconductor structure
US9754881B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9754881-B2 |
| Application number | US-201615050087-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 22, 2016 |
| Priority date | Sep 3, 2014 |
| Publication date | Sep 5, 2017 |
| Grant date | Sep 5, 2017 |
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- Title
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Abstract
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Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate. The gate structures follow the following equation: 0.2 P gate min + 0.35 L gate min + 0.3 H gate min - 20 0.2 L gate min + 0.8 H gate min - 5 × 0.3 L gate min + 0.3 H gate min + 5 38 ≤ 0.32 P gate min is the minimum value among gate pitches of the gate structures, and L gate min is the minimum value among gate lengths of the gate structures. H gate min is the minimum value among gate heights of the gate structures.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor structure, comprising: a plurality of gate structures extending in a first direction formed over a substrate, wherein the gate structures follow the following equation: 0.2 P gate min + 0.35 L gate min + 0.3 H gate min - 20 0.2 L gate min + 0.8 H gate min - 5 × 0.3 L gate min + 0.3 H gate min + 5 38 ≤ 0.32 wherein P gate min is the minimum value among gate pitches of the gate structures; L gate min is the minimum value among gate lengths of the gate structures; and H gate mm is the minimum value among gate heights of the gate structures. 2. The semiconductor structure as claimed in claim 1 , further comprising: a contact formed adjacent to the gate structures over the substrate, wherein the contact has a contact width W contact following the following equation: W contact ≧1.4 L gate min . 3. The semiconductor structure as claimed in claim 1 , further comprising: a plurality of metal layers formed over the gate structures, wherein some of the metal layers comprise metal lines extending in the first direction, and some of the metal layers comprise metal lines extending in a second direction substantially perpendicular to the first direction. 4. The semiconductor structure as claimed in claim 3 , wherein two metal line pitches P metal line of the metal lines in two of the metal layers follow the following equation: P metal line ≦0.76 P gate min . 5. The semiconductor structure as claimed in claim 3 , wherein the metal layers further comprise a first metal layer having first metal lines extending in the first direction, and the first metal layer is the metal layer positioned closest to the gate structure among the metal layers which comprise metal lines extending in the first direction, and pitches of the first metal lines in the first metal layer follow the following equation: P 1st metal line min ≧0.5 P gate min +0.55 L gate min +0.18 H gate min wherein P 1st metal line min is the minimum value among the pitches of the first metal lines in the first metal layer. 6. The semiconductor structure as claimed in claim 3 , wherein the metal layers comprise a first metal layer having first metal lines extending in the first direction, and the first metal layer is the metal layer positioned closest to the gate structures among the metal layers which comprise metal lines extending in the first direction, and at least one of the first metal lines has a thickness T 1st metal line following the following equation: T 1st metal line ≧0.6 P gate min +0.45 L gate min +0.15 H gate min . 7. The semiconductor structure as claimed in claim 3 , wherein the metal layers comprise a first metal layer having first metal lines extending in the first direction, and the first metal layer is the metal layer positioned closest to the gate structures among the metal layers which comprise metal lines extending in the first direction, and at least one of the first metal lines has a width W 1st metal line following the following equation: W 1st metal line ≧0.38 P gate min +0.23 L gate min +0.13 H gate min . 8. The semiconductor structure as claimed in claim 3 , wherein the metal layers comprise a first metal layer having first metal lines extending in the first direction, and the first metal layer is the metal layer positioned closest to the gate structures among the metal layers which comprise metal lines extending in the first direction, and a via connecting to on
Assignees
Inventors
Classifications
Vias, e.g. via plugs · CPC title
- H10W20/43Primary
Layouts of interconnections · CPC title
- H01L23/528Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9754881B2 cover?
- Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate. The gate structures follow the following equation: 0.2 …
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W20/43. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 05 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).