Semiconductor devices including a contact structure and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9754880-B2
Application number	US-201615016376-A
Country	US
Kind code	B2
Filing date	Feb 5, 2016
Priority date	Apr 22, 2015
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

The semiconductor device may include an insulating interlayer on the substrate, the substrate including a contact region at an upper portion thereof, a main contact plug penetrating through the insulating interlayer and contacting the contact region, the main contact plug having a pillar shape and including a first barrier pattern and a first metal pattern, and an extension pattern surrounding on an upper sidewall of the main contact plug, the extension pattern including a barrier material. In the semiconductor device, an alignment margin between the contact structure and an upper wiring thereon may increase. Also, a short failure between the contact structure and the gate electrode may be reduced.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an insulating interlayer on a substrate, the substrate including a contact region at an upper portion thereof;
a main contact plug through the insulating interlayer and in contact with the contact region of the substrate, the main contact plug having a pillar shape and including a first barrier pattern and a first metal pattern; and
an extension pattern surrounding an upper sidewall of the main contact plug, the extension pattern including a barrier material,
wherein a top surface of the first barrier pattern is lower than a top surface of the first metal pattern.

2. The semiconductor device of claim 1 , wherein the first metal pattern has a pillar shape, and the first barrier pattern covers a sidewall and a bottom portion of the first metal pattern.

3. The semiconductor device of claim 1 , wherein a top surface of the main contact plug is substantially coplanar with a top surface of the extension pattern.

4. The semiconductor device of claim 1 , wherein the extension pattern is directly in contact with an upper sidewall of the first metal pattern of the main contact plug.

5. The semiconductor device of claim 1 , wherein substantially all portions of the extension pattern include the barrier material.

6. The semiconductor device of claim 1 , wherein the extension pattern further comprises a second barrier pattern and a second metal pattern.

7. The semiconductor device of claim 6 , wherein the second barrier pattern is in contact with a top surface of the first barrier pattern, an upper sidewall of the first metal pattern and a portion of the insulating interlayer, and wherein the second metal pattern is on the second barrier pattern.

8. The semiconductor device of claim 1 , wherein the barrier material of the extension pattern comprises at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), TiAlC, cobalt (Co), ruthenium (Ru), and nickel (Ni).

9. A semiconductor device, comprising:
a plurality of conductive structures on a substrate, the substrate including a contact region at an upper portion thereof between the conductive structures, at least one of the conductive structures including a conductive pattern and a capping pattern, and the capping pattern surrounding a surface of the conductive pattern;
an insulating interlayer covering the conductive structures on the substrate, a top surface of the insulating interlayer being higher than top surfaces of the conductive structures;
a main contact plug through the insulating interlayer and contacting the contact region, the main contact plug having a pillar shape and including a first barrier pattern and a first metal pattern; and
an extension pattern surrounding an upper sidewall of the main contact plug, the extension pattern including a barrier material,
wherein a top surface of the first barrier pattern is lower than a top surface of the first metal pattern.

10. The semiconductor device of claim 9 , wherein the main contact plug has a first width that is substantially the same as or smaller than a second width of the contact region.

11. The semiconductor device of claim 9 , wherein a bottom of the extension pattern is higher than top surfaces of the conductive structures.

12. The semiconductor device of claim 9 , wherein the extension pattern is apart from and partially overlaps each of the conductive structures vertically.

13. The semiconductor device of claim 9 , wherein each of the conductive structures includes a structure and a spacer on a sidewall of the structure, the structure including a gate insulation pattern, a gate electrode and a hard mask sequentially stacked.

14. The semiconductor device of claim 13 , wherein the gate electrode includes a metal, and the gate insulation pattern covers a sidewall and a bottom of the gate electrode.

15. The semiconductor device of claim 9 , wherein the barrier material of the extension pattern comprises at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), TiAlC, cobalt (Co), ruthenium (Ru), and nickel (Ni).

16. A contact structure of a semiconductor device, comprising:
an insulating interlayer on at least one contact region of a substrate, the insulating interlayer including a first insulating interlayer and a second insulating interlayer;
a plurality of gate structures on the substrate and formed in the first insulating interlayer;
at least one main contact plug through the first and second insulating interlayers and in contact with the at least one contact region of the substrate between adjacent ones of the plurality of gate structures, the at least one main contact plug not overlapping the plurality of gate structures in a direction substantially perpendicular to a surface of the substrate; and
at least one contact extension pattern surrounding at least one upper sidewall of the at least one main contact plug,
wherein the at least one main contact plug has a pillar shape and includes a first barrier pattern and a first metal pattern, and
wherein a top surface of the first barrier pattern is lower than a top surface of the first metal pattern.

17. The contact structure of claim 16 , wherein the contact extension pattern is directly in contact with an upper sidewall of the first metal pattern of the main contact plug.

18. The contact structure of claim 16 , wherein the at least one contact extension pattern comprises a barrier material.

19. The contact structure of claim 16 , wherein a top surface of the main contact plug is substantially coplanar with a top surface of the extension pattern.

Assignees

• Baek Jae-Jik
• Kwon Kee-Sang
• Park Sang-Jine
• Yoon Bo-Un
• Samsung Electronics Co Ltd

Inventors

• Baek Jae-Jik
• Kwon Kee-Sang
• Park Sang-Jine
• Yoon Bo-Un

Classifications

• H10W20/054

  by selectively removing parts thereof (H10W20/034 takes precedence) · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/425 Primary

  Barrier, adhesion or liner layers · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title