Managing memory regions to support sparse mappings

Patent metadata

Field	Value
Publication number	US-9754561-B2
Application number	US-201314046064-A
Country	US
Kind code	B2
Filing date	Oct 4, 2013
Priority date	Oct 4, 2013
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.

First claim

The invention claimed is:

1. A system configured to manage sparse mappings, the system comprising:
a memory that includes a page table having a plurality of page table entries; and
a memory management unit coupled to the memory for managing sparse mappings and configured to:
select a first page table entry included in the plurality of page table entries based on a first virtual memory address included in a first memory access request,
determine that the first page table entry does not include a mapping associated with the first virtual memory address,
determine that the first page table entry is associated with an active sparse status,
set a physical memory address requested for the first virtual memory address to a first physical memory address if the first memory access request comprises a write operation involving the first virtual memory address,
set the physical memory address requested for the first virtual memory address to a second physical memory address if the first memory access request comprises a non-write operation involving the first virtual memory address, and
generate an acknowledgement of the first memory access request.

2. The system of claim 1 , wherein an active status bit included in the first page table entry indicates that the first page table entry is associated with the active sparse status.

3. The system of claim 1 , wherein the memory further includes a page directory that includes a first page directory entry that specifies the page table, and an active status bit included in the first page directory entry indicates that the first page table entry is associated with the active sparse status.

4. The system of claim 1 , wherein the first request is a write operation, and wherein setting the physical memory address requested for the first virtual memory address comprises determining a physical address associated with a sparse write page that is included in the memory.

5. The system of claim 4 , wherein the memory management unit is further configured to:
receive a second request to translate a second virtual memory address to a physical memory address, wherein the second request also is a write operation,
select a second page table entry included in the plurality of page table entries based on the second virtual memory address,
determine that the second page table entry does not include a mapping that is associated with the second virtual memory address,
determine that the second page table entry is associated with the active sparse status,
set the physical memory address requested for the second virtual memory address to a physical address associated with the sparse write page, and
generate an acknowledgement of the second request.

6. The system of claim 1 , wherein the first request is at least one of a read operation and an atomic operation, and wherein setting the physical memory address requested for the first virtual memory address comprises determining a physical address associated with a zero-filled sparse read page included in the memory.

7. The system of claim 6 , wherein the memory management unit is further configured to:
receive a second request to translate a second virtual memory address to a physical memory address, wherein the second request is at least one of a read operation and an atomic operation,
select a second page table entry based on the second virtual memory address,
determine that the second page table entry does not include a mapping that is associated with the second virtual memory address,
determine that the second page table entry is associated with the active sparse status,
set the physical memory address requested for the second virtual memory address to a physical address associated with the zero-filled sparse read page, and
generate an acknowledgement of the second request.

8. The system of claim 1 , wherein the memory management unit is further configured to set a sparse status field associated with the acknowledgement of the first request to indicate that the first page table entry is associated with the active sparse status.

9. The system of claim 8 , further comprising:
a texture unit that is coupled to the memory management unit and is configured to:
receive the acknowledgement of the first request from the memory management unit, and
update a data cache based on the sparse status field associated with the acknowledgement of the first request.

10. A computer-implemented method for managing sparse mappings, the method comprising:
accessing a page table having a plurality of page table entries, wherein the page table is included in a memory;
selecting a first page table entry included in the plurality of page table entries based on a first virtual memory address included in a first memory access request;
determining that the first page table entry does not include a first mapping associated with the first virtual memory address;
determining that the first page table entry is associated with an active sparse status;
setting a physical memory address requested for the first virtual memory address to a first physical memory address if the first memory access request comprises a write operation involving the first virtual memory address;
setting the physical memory address requested for the first virtual memory address to a second physical memory address if the first memory access request comprises a non-write operation involving the first virtual memory address; and
generating an acknowledgement of the first request;
generate an acknowledgement of the first memory access request.

11. The method of claim 10 , wherein an active status bit included in the first page table entry indicates that the first page table entry is associated with the active sparse status.

12. The method of claim 10 , wherein the memory further includes a page directory that includes a first page directory entry that specifies the page table, and an active status bit included in the first page directory entry indicates that the first page table entry is associated with the active sparse status.

13. The method of claim 10 , wherein the first request is a write operation, and wherein setting the first physical memory address requested for the first virtual memory address comprises determining a physical address associated with a sparse write page that is included in the memory.

14. The method of claim 13 , further comprising:
receiving a second request to translate a second virtual memory address to a physical memory address, wherein the second request also is a write operation;
selecting a second page table entry included in the plurality of page table entries based on the second virtual memory address;
determining that the second page table entry does not include a second mapping that is associated with the second virtual memory address;
determining that the second page table entry is associated with the active sparse status;
setting the physical memory address requested for the second virtual memory address to a physical address associated with the sparse write page; and
generating an acknowledgement of the second request.

15. The method of claim 10 , wherein the first request is at least one of a read operation and an atomic operation, and wherein setting the physical memory address requested for the first virtual memory address comprises determining a physical address associated with a zero-filled sparse read page included in the memory.

16. The method of claim 15 , further comprising:
receiving a second request to translate a second virtual memory address to a physical memory address, wherein the second reque

Assignees

• Nvidia Corp

Inventors

• Dunaisky Jonathan
• Moreton Henry Packard
• Bolz Jeffrey A
• Uralsky Yury Y
• Deming James Leroy
• Bastos Rui M
• Brown Patrick R
• Grewal Amanpreet
• Amsinck Christian
• Rao Poornachandra
• Duluk Jr Jerome F
• Tao Andrew J

Classifications

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G09G5/39 Primary

  Control of the bit-mapped memory · CPC title

• G06T1/60

  Memory management · CPC title