System for selecting a task to be executed according to an output from a task control circuit

Patent metadata

Field	Value
Publication number	US-9753729-B2
Application number	US-201615098992-A
Country	US
Kind code	B2
Filing date	Apr 14, 2016
Priority date	Aug 24, 2006
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

The speed of task scheduling by a multitask OS is increased. A task processor includes a CPU, a save circuit, and a task control circuit. The CPU is provided with a processing register and an execution control circuit operative to load data from a memory into a processing register and execute a task in accordance with the data in the processing register. The save circuit is provided with a plurality of save registers respectively associated with a plurality of tasks. In executing a predetermined system call, the execution control circuit notifies the task control circuit as such. The task control circuit switches between tasks for execution upon receipt of the system call signal, by saving, in the save register associated with a task being executed, the data in the processing register, selecting a task to be executed next, and loading data in the save register associated with the selected task into the processing register.

First claim

The invention claimed is:

1. A task processing method to be executed by a processor and a task control circuit, the processor being connected, via a plurality of data lines, with a plurality of save registers fixedly associated one-to-one with a plurality of tasks, the method comprising:
operating the processor to:
load an instruction and an operand from a memory into a processing register;
determine, by hardware logic, whether the instruction loaded into the processing register is a predetermined system call instruction or not; and
transmit a predetermined system call signal to the task control circuit when executing the predetermined system call instruction, the predetermined system call signal not including any information regarding which task to be executed next, and

operating the task control circuit to switch between tasks for execution autonomously by:
saving data stored in the processing register into a save register via a data line associated with the save register, the save register being associated with a task being executed, upon receipt of the predetermined system call signal;
selecting the task to be executed next by not referring to the system call signal but by referring to context information of each task; and
loading data in the save register associated with the selected task into the processing register via the data line associated with the save register.

2. The task processing method of claim 1 , wherein the processor halts supply of a clock for advancing execution of the task when executing the predetermined system call, and resumes the clock after the data has been loaded from the save register associated with the selected task into the processing register.

3. The task processing method of claim 2 , wherein the processor halts the clock while a plurality of instructions are subjected to a pipeline process, the processor halting the clock on the condition that the execution of another instruction when the predetermined system call is being executed reaches a predetermined phase that can be suspended.

4. The task processing method of claim 2 , wherein
the task control circuit transmits a halt request signal to the processor upon receipt of an interrupt request signal from an external device, and
the processor executes an interrupt task associated with the interrupt request signal upon receipt of the interrupt request signal by halting the clock, loading data for execution of the interrupt task into the processing register, and then resuming the supply of the clock.

5. The task processing method of claim 2 , wherein in the presence of another instruction being executed when executing the predetermined system call, the processor halts the clock while a plurality of instructions are subjected to a pipeline process and saves an interim result of processing the another instruction in the save registers.

6. The task processing method of claim 1 , wherein the data in the processing register is continuously output to the plurality of save registers, and the processor feeds a write signal to the save register associated with the task being executed so as to save the data in the processing register into the associated save register.

7. The task processing method of claim 1 , wherein
the data in the plurality of save registers is continuously output, and
the processor transmits an output signal designating the save register associated with the task selected for execution to a selector circuit, thereby loading the data in the associated save register into the processing register.

8. The task processing method of claim 1 , wherein the processing register and the plurality of save registers are connected via a bus carrying the number of bits capable of transmitting the data in the processing register in parallel.

9. A task processing method to be executed by a processor and a task control circuit, the processor being connected, via a plurality of data lines, with a plurality of save registers fixedly associated one-to-one with a plurality of tasks, the method comprising:
switching between tasks for execution autonomously by:
operating the processor to:
load an instruction and an operand from a memory into a processing register; and
determine, by hardware logic, whether the instruction loaded into the processing register is a predetermined system call instruction or not; and

operating the task control circuit to
save data stored in the processing register into a save register via a data line associated with the save register, the save register being associated with a task being executed among a plurality of save registers associated with a plurality of tasks, in execution of the predetermined system call instruction;
detect, by hardware logic, the task to be executed next by referring to context information of each task; and
load data in the save register associated with the selected task into the processing register via the data line associated with the save register.

Assignees

• Renesas Electronics Corp

Inventors

• Maruyama Naotaka

Classifications

• G06F9/52 Primary

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title

• G06F9/4806 Primary

  Task transfer initiation or dispatching · CPC title

• G06F9/462

  with multiple register sets · CPC title

• G06F9/30079

  Pipeline control instructions, e.g. multicycle NOP · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title