Fabrication of nanomaterial T-gate transistors with charge transfer doping layer

Patent metadata

Field	Value
Publication number	US-9748334-B1
Application number	US-201615046723-A
Country	US
Kind code	B1
Filing date	Feb 18, 2016
Priority date	Feb 18, 2016
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A field effect transistor including a dielectric layer on a substrate, a nano-structure material (NSM) layer on the dielectric layer, a source electrode and a drain electrode formed on the NSM layer, a gate dielectric formed on at least a portion of the NSM layer between the source electrode and the drain electrode, a T-shaped gate electrode formed between the source electrode and the drain electrode, where the NSM layer forms a channel of the FET, and a doping layer on the NSM layer extending at least from the sidewall of the source electrode to a first sidewall of the gate dielectric, and from a sidewall of the drain electrode to a second sidewall of the gate dielectric.

First claim

What is claimed is:

1. A method of fabricating a nanostructure material field effect transistor (NSM FET) comprising:
forming a NSM layer on at least a portion of a dielectric layer;
forming a source electrode and a drain electrode on at least a portion of the NSM layer;
forming a gate dielectric on at least a portion of the NSM layer between the source electrode and the drain electrode;
forming a T-shaped gate electrode between the source electrode and the drain electrode on the gate dielectric, wherein the NSM layer forms a channel of the FET, and the T-shaped gate electrode is formed by forming sacrificial spacer material on exposed portions of the NSM layer; and
forming a doping layer directly on the surface of the NSM layer, where the doping layer extends at least from a sidewall of the source electrode to a first sidewall of the gate dielectric, and at least from a sidewall of the drain electrode to a second sidewall of the gate dielectric, wherein the gate dielectric is deposited over the sacrificial spacer material and the NSM layer, the T-shaped gate electrode material is deposited on the gate dielectric, the T-shaped gate electrode material and the gate dielectric are patterned and removed to form a gate electrode having a bottom surface with a width in the range of about 5 nm to about 500 nm, and a top surface with a width and surface area greater than the bottom surface of the T-shaped gate electrode, and the sacrificial spacer material is removed.

2. The method of fabricating the NSM FET of claim 1 , wherein the NSM layer includes carbon (C), boro-carbon nitrides (e.g., BC 2 N), transition metal dichalcogenides, group IV semiconductors, II-VI semiconductors, or III-V semiconductors.

3. The method of fabricating the NSM FET of claim 1 , wherein the NSM layer includes single-walled nanotubes (SWNTs), double-walled nanotubes (DWNTs), multi-walled nanotubes (MWNTs), chemically modified nanotubes, 2-dimensional lattice, or semiconducting nanowires.

4. The field effect transistor of claim 3 , wherein the SWNTs, DWNTs, MWNTs, and chemically modified nanotubes are carbon SWNTs, carbon DWNTs, carbon MWNTs, chemically modified carbon nanotubes, and the 2-dimensional lattice is graphene.

5. The method of fabricating the NSM FET of claim 1 , wherein the NSM layer is formed by a wet method, where nano-structure material is deposited from a solution.

6. The method of fabricating the NSM FET of claim 1 , further comprising functionalizing the surface of the dielectric layer to increase adhesion of the NSM layer, and/or forming a wetting layer on at least a portion of the NSM layer to increase adhesion of the source and drain electrodes.

7. The method of fabricating the NSM FET of claim 6 , wherein the doping layer includes benzyl viologen, silicon nitride, silicon oxynitride, magnesium oxide, aluminum oxide, hafnium oxide, hafnium silicate, hafnium silicon oxynitride, triethyloxonium hexachloroantimonate ((CH 3 CH 2 )O + SbCl 6 − ), or combinations thereof.

8. The method of fabricating the NSM FET of claim 1 , wherein the doping layer is isotropically applied by ALD, CVD, or a wet deposition.

9. The method of fabricating the NSM FET of claim 1 , wherein a first extension region is formed between the T-shaped gate electrode and the source electrode, and a second extension region is formed between the T-shaped gate electrode and the drain electrode, wherein the doping layer covers the entire extension region between the source electrode and the T-shaped gate electrode, and the entire extension portion between the drain electrode and the T-shaped gate electrode.

10. A method of fabricating a nanostructure material field effect transistor (NSM FET) comprising:
forming a dielectric layer on at least a portion of a substrate;
forming a NSM layer on at least a portion of dielectric layer, wherein the NSM layer includes single-walled carbon nanotubes (SWNTs), double-walled carbon nanotubes (DWNTs), multi-walled carbon nanotubes (MWNTs), chemically modified carbon nanotubes, or graphene;
patterning the NSM layer to leave gaps between adjacent sections of NSM material to form a plurality of isolated active areas;
forming a source electrode and a drain electrode on at least a portion of the NSM layer forming an isolated active area;
forming a gate dielectric on the portion of the NSM layer between the source electrode and the drain electrode;
forming a T-shaped gate electrode between the source electrode and the drain electrode on the gate dielectric, wherein the NSM layer forms a channel of the FET, and the T-shaped gate electrode is formed by forming sacrificial spacer material on exposed portions of the NSM layer; and
forming a doping layer directly on the surface of the NSM layer, where the doping layer extends at least from a sidewall of the source electrode to a first sidewall of the gate dielectric, and at least from a sidewall of the drain electrode to a second sidewall of the gate dielectric, wherein the gate dielectric is deposited over the sacrificial spacer material and the NSM layer, the T-shaped gate electrode material is deposited on the gate dielectric, the T-shaped gate electrode material and the gate dielectric are patterned and removed to form a gate electrode having a bottom surface with a width in the range of about 5 nm to about 500 nm, and a top surface with a width and surface area greater than the bottom surface of the T-shaped gate electrode, and the sacrificial spacer material is removed.

Assignees

• IBM

Inventors

• Bangsaruntip Sarunya
• Engel Michael
• Han Shu-Jen

Classifications

• H10P14/26

  using liquid deposition · CPC title

• H10D64/01324

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H10D64/0125

  characterised by the sectional shape, e.g. T or inverted T · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W74/43

  comprising oxides, nitrides or carbides, e.g. ceramics or glasses · CPC title