Semiconductor integrated circuits having contacts spaced apart from active regions

Patent metadata

Field	Value
Publication number	US-9748246-B2
Application number	US-201514877247-A
Country	US
Kind code	B2
Filing date	Oct 7, 2015
Priority date	Nov 6, 2014
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

First and second active regions are doped with different types of impurities, and extend in a first direction and spaced apart from each other in a second direction. First and third gate structures, which are on the first active region and a first portion of the isolation layer between the first and second active regions, extend in the second direction and are spaced apart from each other in the first direction. Second and fourth gate structures, which are on the second active region and the first portion, extend in the second direction, are spaced apart from each other in the first direction, and face and are spaced apart from the first and third gate structures, respectively, in the second direction. First to fourth contacts are on portions of the first to fourth gate structures, respectively. The first and fourth contacts are connected, and the second and third contacts are connected.

First claim

What is claimed is:

1. A semiconductor integrated circuit, comprising:
first and second active regions defined by an isolation layer on a substrate, the first and second active regions being doped with different types of impurities, the first and second active regions extending in a first direction, and the first and second active regions being spaced apart from each other in a second direction, the second direction being substantially perpendicular to the first direction, wherein
a first portion of the first active region has a first width in the second direction, and a second portion of the first active region has a second width in the second direction, the first width different from the second width;

a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure, wherein
the first gate structure is on the first portion of the first active region and a first portion of the isolation layer between the first and second active regions,
the third gate structure is on the second portion of the first active region and the first portion of the isolation layer between the first and second active regions,
the first and third gate structures extend in the second direction, and the first and third gate structures are spaced apart from each other in the first direction, and
the second and the fourth gate structures are on the second active region and the first portion of the isolation layer, the second and fourth gate structures extend in the second direction, the second and fourth gate structures are spaced apart from each other in the first direction, and the second and fourth gate structures face and are spaced apart from the first and third gate structures, respectively, in the second direction; and

a first contact, a second contact, a third contact, and a fourth contact, the first to fourth contacts between the first and second active regions, and the first to fourth contacts being on portions of the first to fourth gate structures, respectively, wherein
the first and fourth contacts are electrically connected to each other,
the second and third contacts are electrically connected to each other,
the first and third contacts are spaced apart from the first active region in the second direction by substantially the same distance, and
the second and fourth contacts are spaced apart from the second active region in the second direction by substantially the same distance.

2. The semiconductor integrated circuit of claim 1 , wherein
the first active region is doped with p-type impurities; and
the second active region is doped with n-type impurities.

3. The semiconductor integrated circuit of claim 1 , wherein the first and fourth contacts are electrically connected to each other through a first lower wiring on the first and fourth contacts.

4. The semiconductor integrated circuit of claim 1 , further comprising:
a first impurity region, a second impurity region, a third impurity region, and a fourth impurity region, wherein
the first and third impurity regions are at upper portions of the first active region at opposite sides of the first gate structure, respectively, and the first and third impurity regions are doped with impurities of a first conductivity type, and
the second and fourth impurity regions are at upper portions of the second active region at opposite sides of the second gate structure, respectively, and the second and fourth impurity regions are doped with impurities of a second conductivity type.

5. The semiconductor integrated circuit of claim 1 , further comprising:
a fifth gate structure on the first active region and the first portion of the isolation layer, the fifth gate structure extending in the second direction, and being spaced apart from the third gate structure in the first direction; and
a sixth gate structure on the second active region and the first portion of the isolation layer, the sixth gate structure extending in the second direction, and being spaced apart from the fourth gate structure in the first direction, wherein
the fifth and sixth gate structures are connected to each other on the first portion of the isolation layer, and
the fifth and sixth gate structures extend in the second direction.

6. The semiconductor integrated circuit of claim 1 , wherein each of the first to fourth gate structures is configured to receive a clock signal from among a plurality of clock signals.

7. The semiconductor integrated circuit of claim 3 , further comprising:
a second lower wiring on the second contact;
a third lower wiring on the third contact;
a first via on the second lower wiring;
a second via on the third lower wiring; and
a first upper wiring on both of the first and second vias, wherein
the second and third contacts are electrically connected to each other through the second and third lower wirings, the first and second vias, and the first upper wiring.

8. The semiconductor integrated circuit of claim 4 , further comprising:
fifth and sixth contacts on the first and second impurity regions, respectively, the fifth and sixth contacts being electrically connected to each other.

9. The semiconductor integrated circuit of claim 4 , further comprising:
fifth and sixth contacts on the third and fourth impurity regions, respectively, the fifth and sixth contacts being electrically connected to each other.

10. A semiconductor integrated circuit, comprising:
first and second active regions defined by an isolation layer on a substrate, the first and second active regions being doped with different types of impurities, the first and second active regions extending in a first direction, and the first and second active regions being spaced apart from each other in a second direction, the second direction being substantially perpendicular to the first direction, wherein
a first portion of the first active region has a first width in the second direction, and a second portion of the first active region has a second width in the second direction, the first width different from the second width;

a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure, wherein
the first gate structure is on the first portion of the first active region and a first portion of the isolation layer adjacent to the first active region,
the third gate structure is on the second portion of the first active region and the first portion of the isolation layer adjacent to the first active region,
the first and third gate structures extend in the second direction, and the first and third gate structures are spaced apart from each other in the first direction, and
the second and fourth gate structures are on the second active region and a second portion of the isolation layer adjacent to the second active region, the second and fourth gate structures extend in the second direction, the second and fourth gate structures are spaced apart from each other in the first direction, and the second and fourth gate structures face and are spaced apart from the first and third gate structures, respectively, in the second direction; and

a first contact, a second contact, a third contact, and a fourth contact, the first to fourth contacts being on portions of the first to fourth gate structures, respectively, wherein
the first and fourth contacts are electrically connected to each other,
the second and third contacts are electrically connected to each other,
the first and third contacts are spaced apart from a same first boundary at a same first side of the first active region in the second direction by substantially the same distance, and
the second and fourth contacts are spaced apart from a same second bounda

Assignees

• Song Tae-Joong
• Kim Jung-Han
• Samsung Electronics Co Ltd

Inventors

• Song Tae-Joong
• Kim Jung-Han

Classifications

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H01L27/092

  Electricity · mapped topic

• H03K3/356156

  with synchronous operation · CPC title

• H01L27/0928 Primary

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic