Packages Having Integrated Devices and Methods of Forming Same
US-2016056100-A1 · Feb 25, 2016 · US
Dual-sided silicon integrated passive devices
US9748227B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9748227-B2 |
| Application number | US-201615057588-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 1, 2016 |
| Priority date | Jul 15, 2015 |
| Publication date | Aug 29, 2017 |
| Grant date | Aug 29, 2017 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the integrated circuit to a circuit board. The integrated circuit may include a semiconductor die coupled to the second surface of the substrate using a second set of electrical conductors. The integrated circuit may include a passive device dimensioned to be integrated with the integrated circuit. The passive device may be positioned between the second surface and at least one of the first set of electrical conductors. The die may be electrically connected to a second side of the passive device. A first side of the passive device may be available to be electrically connected to a second device.
First claim
Opening claim text (preview).
What is claimed is: 1. An integrated circuit, comprising: a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface configured to electrically connect the integrated circuit to a circuit board; a semiconductor die coupled to the second surface of the substrate using a second set of electrical conductors; and a passive device dimensioned to be integrated with the integrated circuit, wherein the passive device is positioned between the first surface and at least one of the first set of electrical conductors, such that the first surface and the at least one of the first set of electrical conductor directly contact the passive device. 2. The integrated circuit of claim 1 , wherein the passive device is coupled to the first surface of the substrate. 3. The integrated circuit of claim 1 , wherein the passive device is incapable of controlling current by means of another electrical signal. 4. The integrated circuit of claim 1 , wherein the passive device comprises a capacitor or an inductor. 5. The integrated circuit of claim 1 , wherein the passive device comprises a multilayer capacitor. 6. The integrated circuit of claim 1 , wherein the substrate further include conductors to connect the second surface of the substrate to the first surface of the substrate and devices coupled to the first and second surfaces. 7. The integrated circuit of claim 1 , wherein the passive device comprises a thin film inductor. 8. A method of manufacturing an integrated circuit, comprising: coupling a first set of electrical conductors to a first surface of a substrate, wherein the first set of electrical conductors electrically connect the integrated circuit to a circuit board, and wherein the substrate includes a second surface substantially opposite of the first surface; coupling a semiconductor die to the second surface of the substrate using a second set of electrical conductors; integrating a passive device with the integrated circuit, wherein the passive device is positioned between the first surface and at least one of the first set of electrical conductors, such that the first surface and the at least one of the first set of electrical conductors directly contact the passive device. 9. The method of claim 8 , wherein the passive device is incapable of controlling current by means of another electrical signal. 10. The method of claim 8 , wherein the passive device comprises a capacitor or an inductor. 11. The method of claim 8 , wherein the passive device comprises a multilayer capacitor.
Assignees
Inventors
Classifications
Manufacture or treatment · CPC title
the encapsulations exposing the passive side of the semiconductor body · CPC title
on encapsulations · CPC title
Dispositions, e.g. layouts · CPC title
Package configurations · CPC title
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9748227B2 cover?
- In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the integrated circuit to a circuit board. The in…
- Who is the assignee on this patent?
- Apple Inc
- What technology area does this patent fall under?
- Primary CPC classification H01L27/0641. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 29 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).