Package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9748179-B2
Application number	US-201514810947-A
Country	US
Kind code	B2
Filing date	Jul 28, 2015
Priority date	Jul 30, 2014
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

The package includes: a substrate having at least one circuit layer; at least one electronic component mounted on at least one surface of the substrate; a molded part formed on the surface of the substrate to enclose the electronic component; at least one via formed in the molded part to be electrically connected to the circuit layer of the substrate; and a pattern connected to one end of a plated tail connected to the circuit layer connected to the via and exposed to the exterior of the substrate.

First claim

What is claimed is:

1. A package comprising:
a substrate having a wiring pattern deposited on a first surface thereof, the wiring pattern having a plated tail;
an electronic component mounted on the wiring pattern;
a molded part provided on the first surface of the substrate to enclose the electronic component;
a via provided in the molded part to be connected to the plated tail;
a shielding part encasing the substrate, the electronic component, and the molded part, leaving a second surface of the substrate exposed; and
a nonconductive pattern coplanar with the wiring pattern and plated tail, the nonconductive pattern extending between and in physical contact with both the plated tail and the shielding part.

2. The package of claim 1 , wherein the wiring pattern connected to the via is provided with a via pad in surface-contact with the via.

3. The package of claim 1 , wherein the wiring pattern has a circuit pattern which is exposed to the exterior of the substrate.

4. The package of claim 3 , wherein the circuit pattern is a ground electrode.

5. The package of claim 4 , wherein the ground electrode is provided on an edge of the substrate.

6. A package comprising:
a substrate having a wiring pattern deposited on a first surface thereof, the wiring pattern having a plated tail;
an electronic component mounted on the wiring pattern;
a molded part provided on the first surface of the substrate to enclose the electronic component;
a via provided in the molded part to be connected to the plated tail;
a shielding part encasing the substrate, the electronic component, and the molded part, leaving a second surface of the substrate exposed;
a nonconductive pattern coplanar with the wiring pattern and the plated tail, the nonconductive pattern extending between and in physical contact with both the plated tail and the shielding part;
a solder bump provided on the via where the via is exposed from the second surface of the substrate; and
a lower package mounted on the solder bump.

Assignees

• Samsung Electro Mech

Inventors

• Yoo Do Jae
• Oh Kyu Hwan
• Ryu Jong In
• Lim Jae Hyun

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title