Method of fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-9748144-B1
Application number	US-201615138228-A
Country	US
Kind code	B1
Filing date	Apr 26, 2016
Priority date	Apr 26, 2016
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

First and second semiconductor structures, a CESL, and an ILD layer are formed on a substrate. The first semiconductor structure includes first dummy gate, first nitride mask, and first oxide mask. The second semiconductor structure includes second dummy gate, second nitride mask, and second oxide mask. A first planarization is performed to remove a portion of the ILD layer, exposing CESL. A portion of the CESL, a portion of the ILD layer, the first and the second oxide masks are removed. A hard mask layer is formed on the first and the second nitride masks, and in a recess of the ILD layer. A second planarization is performed to remove a portion of the hard mask layer, the first and the second nitride masks, exposing first and second dummy gates. A remaining portion of the hard mask layer covers the ILD layer.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
providing a substrate having a first semiconductor structure, a second semiconductor structure, a contact etch stop layer (CESL) covering the first semiconductor structure and the second semiconductor structure, an inter-layer dielectric (ILD) layer covering the CESL, wherein the first semiconductor structure comprises a first dummy gate, a first nitride mask on the first dummy gate, and a first oxide mask on the first nitride mask, wherein the second semiconductor structure comprises a second dummy gate, a second nitride mask on the second dummy gate, and a second oxide mask on the second nitride mask;
performing a first planarization process to remove a first portion of the ILD layer, thereby exposing a top surface of the CESL;
then removing a portion of the CESL, a second portion of the ILD layer, the first oxide mask, and the second oxide mask to expose the first nitride mask and the second nitride mask;
then removing a third portion of the ILD layer to form a recess in the remaining ILD layer between the first semiconductor structure and the second semiconductor structure;
then forming a hard mask layer on the remaining first nitride mask, the remaining second nitride mask and the remaining ILD layer, wherein the hard mask layer fills up the recess;
then performing a second planarization process to remove a portion of the hard mask layer, the remaining first nitride mask and the remaining second nitride mask, thereby exposing a top surface of the first dummy gate and a top surface of the second dummy gate, wherein a remaining portion of the hard mask layer covers a top surface of the remaining ILD layer between the first semiconductor structure and the second semiconductor structure;
then removing the first dummy gate and the second dummy gate to form a first gate trench and a second gate trench; and
then forming a first metal gate in the first gate trench and a second metal gate in the second gate trench.

2. The method according to claim 1 , wherein the ILD layer is a Flowable CVD (FCVD) oxide layer.

3. The method according to claim 1 , wherein the first dummy gate and the second dummy gate comprise amorphous silicon or polysilicon.

4. The method according to claim 1 , wherein the remaining portion of the hard mask layer completely covers the top surface of the remaining ILD layer between the first semiconductor structure and the second semiconductor structure.

5. The method according to claim 4 , wherein the remaining portion of the hard mask layer is in direct contact with the CESL.

6. The method according to claim 1 , wherein the remaining portion of the hard mask layer partially covers the top surface of the remaining ILD layer between the first semiconductor structure and the second semiconductor structure.

7. The method according to claim 6 , wherein the remaining portion of the hard mask layer is not in physical contact with the CESL.

8. The method according to claim 1 , wherein the first metal gate and the second metal gate have different gate lengths.

9. The method according to claim 8 , wherein the first semiconductor structure is a core FinFET having a gate length less than or equal to 20 nm, and the second semiconductor structure is a peripheral FinFET having a gate length greater than 20 nm.

10. The method according to claim 1 , wherein the hard mask layer comprises silicon nitride.

11. The method according to claim 1 , wherein the ILD layer and the CESL completely fill up a space between the first semiconductor structure and the second semiconductor structure.

12. The method according to claim 1 , wherein the first semiconductor structure further comprises a first spacer on a sidewall of the first dummy gate and the second semiconductor structure further comprises a second spacer on a sidewall of the second dummy gate.

13. The method according to claim 1 , wherein the first semiconductor structure further comprises a first interfacial layer between the first dummy gate and the substrate, and the second semiconductor structure further comprises a second interfacial layer between the second dummy gate and the substrate.

14. The method according to claim 13 , wherein forming the first metal gate in the first gate trench and the second metal gate in the second gate trench comprises:
removing the first interfacial layer and the second interfacial layer to expose the substrate from the first gate trench and the second gate trench respectively;
forming a chemical oxide layer on the substrate exposed from the first gate trench and the second gate trench;
forming a high-k dielectric layer in the first gate trench and in the second gate trench;
forming a work function metal layer on the high-k dielectric layer;
forming a tungsten layer on the work function metal layer; and
performing a third planarization process to remove a portion of the tungsten layer, a portion of the work function metal layer and a portion of the high-k dielectric layer.

Assignees

• United Microelectronics Corp

Inventors

• Lin Ching-Ling
• Chen Yi-Wen
• Huang Chen-Ming
• Huang Ren-Peng
• Lin Ching-Fu

Classifications

• H01L21/823431

  Electricity · mapped topic

• H01L21/823456 Primary

  Electricity · mapped topic

• H01L21/28079

  Electricity · mapped topic

• H01L27/1104

  Electricity · mapped topic

• H01L21/32115

  Electricity · mapped topic