Reference architecture in a cross-point memory

Patent metadata

Field	Value
Publication number	US-9747978-B2
Application number	US-201514850152-A
Country	US
Kind code	B2
Filing date	Sep 10, 2015
Priority date	Jun 24, 2014
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (V REF ) utilizing charge on the selected GWL and charge on the first sense circuitry capacitance and determine a state of the target memory cell based, at least in part, on V REF and a detected memory cell voltage V LWL .

First claim

What is claimed is:

1. An apparatus comprising:
a memory controller configured to select a target memory cell for a memory access operation, the memory controller comprising:
word line (WL) switch circuitry and bit line (BL) switch circuitry configured to select one or more WL and/or BL associated with the target memory cell; and
sense circuitry configured to precharge one or more of the selected WL and/or BL to a WL and/or BL bias voltage, produce a reference voltage (V REF ) utilizing charge on the selected WL and/or BL and an inherent capacitance associated with the charged WL and/or BL and determine a state of the target memory cell based, at least in part, on V REF and a detected memory cell voltage V DET .

2. The apparatus of claim 1 , wherein the inherent capacitance is an inherent capacitance associated with said WL.

3. The apparatus of claim 2 , wherein the inherent capacitance associated with at least a portion of a global WL (GWL).

4. The apparatus of claim 1 , wherein sense circuitry is configured to precharge a selected global WL (GWL) and a local WL (LWL) to a WL bias voltage WLVDM and wherein the BL switch circuitry is configured to apply a BL bias voltage (BLVDM) to a selected local BL (LBL).

5. The apparatus of claim 1 , further comprising an adjustment capacitance, wherein V REF is based, at least in part, on the adjustment capacitance.

6. The apparatus of claim 5 , wherein the adjustment capacitance comprises at least one of trim capacitor circuitry and an unselected global WL (GWL).

7. The apparatus of claim 1 , further comprising a sense amplifier comprising a first input coupled to a second sense circuitry capacitance and a second input coupled to a first sense circuitry capacitance, the sense circuitry configured to couple the first input to the second input to produce V REF .

8. The apparatus of claim 7 , wherein the sense amplifier is configured to receive a sensed voltage (V SENSE ) related to V REF and V DET , to level shift V SENSE and V REF to intermediate positive-referenced voltages and to convert the intermediate voltages to a logic level output that corresponds to the state of the target memory cell.

9. A method comprising:
precharging, by sense circuitry, a selected word line (WL) and/or bit line (BL) to a WL and/or BL bias voltage;
producing, by the sense circuitry, a reference voltage (V REF ) utilizing charge on the selected WL and/or BL and an inherent capacitance associated with the charged WL and/or BL; and
determining, by the sense circuitry, a state of the target memory cell based, at least in part, on V REF and a detected memory cell voltage V DET .

10. The method of claim 9 , wherein V REF is based, at least in part, on an adjustment capacitance.

11. The method of claim 10 , wherein the adjustment capacitance comprises at least one of trim capacitor circuitry and an unselected global WL (GWL).

12. The method of claim 9 , further comprising:
coupling, by the sense circuitry, a first input of a sense amplifier to a second input of the sense amplifier to produce V REF , the first input coupled to a second sense circuitry capacitance and the second input coupled to a first sense circuitry capacitance.

13. The method of claim 12 , further comprising:
receiving, by the sense amplifier, a sensed voltage (V SENSE ) related to V REF and V DET ;
level shifting, by the sense amplifier, V SENSE and V REF to intermediate positive-referenced voltages; and
converting, by the sense amplifier, the intermediate voltages to a logic level output that corresponds to the state of the target memory cell.

14. A system comprising:
a processor;
a cross-point memory array comprising a target memory cell, a target word line (WL) and a target bit line (BL), the target memory cell coupled between the target WL and the target BL; and
a memory controller coupled to the processor and the cross-point memory array, the memory controller configured to select a target memory cell for a memory access operation, the memory controller comprising:
word line (WL) switch circuitry and bit line (BL) switch circuitry configured to select one or more WL and/or BL associated with the target memory cell; and
sense circuitry configured to precharge one or more selected WL and/or BL to a WL and/or BL bias voltage, produce a reference voltage (V REF ) utilizing charge on the selected WL and/or BL and an inherent capacitance associated with the charged WL and/or BL and determine a state of the target memory cell based, at least in part, on V REF and a detected memory cell voltage V DET .

15. The system of claim 14 , wherein the inherent capacitance is an inherent capacitance associated with said WL.

16. The system of claim 14 , wherein sense circuitry is configured to precharge a selected global WL (GWL) and a local WL (LWL) to a WL bias voltage WLVDM and wherein the BL switch circuitry is configured to apply a BL bias voltage (BLVDM) to a selected local TL (LBL).

17. The system of claim 14 , further comprising an adjustment capacitance, wherein V REF is based, at least in part, on the adjustment capacitance.

18. The system of claim 17 , wherein the adjustment capacitance comprises at least one of trim capacitor circuitry and an unselected global WL (GWL).

19. The system of claim 14 , further comprising a sense amplifier comprising a first input coupled to a second sense circuitry capacitance and a second input coupled to a first sense circuitry capacitance, the sense circuitry configured to couple the first input to the second input to produce V REF .

20. The system of claim 19 , wherein the sense amplifier is configured to receive a sensed voltage (V SENSE ) related to V REF and V DET , to level shift V SENSE and V REF to intermediate positive-referenced voltages and to convert the intermediate voltages to a logic level output that corresponds to the state of the target memory cell.

Assignees

• Intel Corp

Inventors

• Srinivasan Balaji
• Rivers Doyle
• Kau Derchang
• Goldman Matthew

Classifications

• G11C2213/77

  Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used · CPC title

• G11C13/0004 Primary

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0028

  Word-line or row circuits · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title

• G11C2013/0057

  Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value · CPC title