Methods and systems for verifying cell programming in phase change memory

Patent metadata

Field	Value
Publication number	US-9747977-B2
Application number	US-201313827825-A
Country	US
Kind code	B2
Filing date	Mar 14, 2013
Priority date	Mar 14, 2013
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.

First claim

What is claimed is:

1. A method of verifying cell programming for phase change memory, comprising:
sending a reset pulse to a phase change memory cell;
sensing a first instance of a threshold voltage of the phase change memory cell in response to applying a first verify voltage across the phase change memory cell;
sensing a second instance of the threshold voltage of the phase change memory cell in response to applying a second verify voltage across the phase change memory cell where the second verify voltage is lower than the first verify voltage;
determining whether the first instance of the threshold voltage of the phase change memory cell was above the first verify voltage and the second instance of the threshold voltage of the phase change memory cell was below the second verify voltage; and
determining that the phase change memory cell was disturbed by the first verify voltage if the first instance of the threshold voltage of the phase change memory was above the first verify voltage and the second instance of the threshold voltage of the phase change memory cell was below the second verify voltage.

2. The method of claim 1 , wherein determining whether the first instance of the threshold voltage of the phase change memory cell was above the first verify voltage and the second instance of the threshold voltage was below the second verify voltage comprises determining whether the phase change memory cell has a lowered resistance after application of the first or second verify voltages.

3. The method of claim 1 , wherein the second verify voltage is higher than a set cell threshold voltage.

4. The method of claim 1 , wherein the first verify voltage is lower than a reset cell threshold voltage.

5. The method of claim 1 , further comprising determining that the phase change memory cell was successfully reset when the first and second instance of the threshold voltage of the phase change memory cell was above the first and second verify voltages.

6. The method of claim 1 , wherein the phase change memory cell includes a chalcogenic material.

7. The method of claim 6 , wherein the chalcogenic material is a an amorphous or semi-amorphous state when in a reset state and a crystalline or semi-crystalline state when in a set state.

8. The method of claim 6 , wherein sending a reset pulse to a phase change memory cell involves heating the chalcogenic material.

9. The method of claim 1 , further comprising cyclically performing, a predetermined number of times, sending the reset pulse, sensing the first instance of the threshold voltage, sensing the second instance of the threshold voltage, and determining whether the first instance of the threshold voltage of the phase change memory cell was above the first verify voltage and the second instance of the threshold voltage of the phase change memory cell was below the second verify voltage.

10. The method of claim 9 , wherein a voltage or current of the reset pulse raises for each cyclical operation of sending the reset pulse, sensing the first instance of the threshold voltage, sensing the second instance of the threshold voltage, and determining whether the first instance of the threshold voltage of the phase change memory cell was above the first verify voltage and the second instance of the threshold voltage of the phase change memory cell was below the second verify voltage.

11. A method of verifying cell programming for phase change memory, comprising:
sending a first reset pulse to a phase change memory cell;
sensing a first instance of a threshold voltage of the phase change memory cell in response to applying a first verify voltage across the phase change memory cell;
selecting a second verify voltage such that a probability of disturbing the phase change memory cell is reduced by a predetermined amount as compared with a probability of disturbing the phase change memory cell using the first verify voltage;
sensing a second instance of the threshold voltage of the phase change memory cell in response to applying the second verify voltage across the phase change memory cell where the second verify voltage is lower than the first verify voltage;
determining whether the first instance of the threshold voltage of the phase change memory cell was above the first verify voltage and the second instance of the threshold voltage of the phase change memory cell was below the second verify voltage.

12. The method of claim 11 , further comprising determining that the phase change memory cell was disturbed if the first instance of the threshold voltage was above the first verify voltage and the second instance of the threshold voltage was below the second verify voltage.

13. The method of claim 12 , further comprising determining that the phase change memory cell was successfully reset when the first and second instance of the threshold voltage of the phase change memory cell was above the first and second verify voltages.

14. The method of claim 12 , further comprising:
determining that the phase change memory cell was not successfully reset when the first or second instance of the threshold voltage of the phase change memory cells was not above the first and second verify voltages;
sending a second reset pulse to a phase change memory cell, wherein a voltage or current of the second reset pulse is greater than a voltage or current of the first rest pulse if the phase change memory cell was not successfully reset;
sensing a third instance of a threshold voltage of the phase change memory cell in response to applying the first verify voltage across the phase change memory cell;
sensing a forth instance of the threshold voltage of the phase change memory cell in response to applying the second verify voltage across the phase change memory cell where the second verify voltage is lower than the first verify voltage;
determining whether the third instance of the threshold voltage of the phase change memory cell was above the first verify voltage and the fourth instance of the threshold voltage of the phase change memory cell was below the second verify voltage.

15. The method of claim 14 , further comprising determining that the phase change memory cell was disturbed by the third verify voltage if the first instance of the threshold voltage of the phase change memory was above the first verify voltage and the fourth instance of the threshold voltage of the phase change memory cell was below the second verify voltage.

16. The method of claim 15 , further comprising determining that the phase change memory cell was successfully reset when the third and fourth instance of the threshold voltage of the phase change memory cell was above the first and second verify voltages.

17. The method of claim 15 , further comprising determining that the phase change memory cell was not successfully reset when the third and fourth instance of the threshold voltage of the phase change memory cells was not above the first and second verify voltages.

18. The method of claim 11 , wherein the second verify voltage is higher than a set cell threshold voltage.

19. The method of claim 11 , wherein the first verify voltage is lower than a reset cell threshold voltage.

20. The method of claim 11 , wherein determining whether the first instance of the threshold voltage of the phase change memory cell was above the first verify voltage and the second instance of the threshold voltage of the phase change memory cell was below the second verify voltage includes determining whether the phase change memory cel

Assignees

• Chu Daniel J
• Zeng Raymond W
• Rivers Doyle
• Intel Corp

Inventors

• Chu Daniel J
• Zeng Raymond W
• Rivers Doyle

Classifications

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C13/0064

  Verifying circuits or methods · CPC title

• G11C13/0033

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C13/0004 Primary

  comprising amorphous/crystalline phase transition cells · CPC title