Data processing device

Patent metadata

Field	Value
Publication number	US-9747232-B2
Application number	US-201514640224-A
Country	US
Kind code	B2
Filing date	Mar 6, 2015
Priority date	Mar 19, 2014
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A data processing device includes: multiple data processing stages including a processing element, a stage memory and an event controller; and a bidirectional slotted bus connecting between the data processing stages, including two write only busses arranged at different data writing directions independently from each other. The processing element and the stage memory in one data processing stage are connected to each other via a read only bus. The processing element and the slotted bus are connected to each other via a write only bus. A process completion event is input from the processing element to the event controller, and an external event is input from an external device to the event controller. The event controller generates a task start event with respect to the processing element, according to each of the process completion event and the external event.

First claim

What is claimed is:

1. A data processing device comprising:
a plurality of data processing stages, each of which includes at least one processing element, at least one stage memory and an event controller; and
a bidirectional slotted bus that connects between the data processing stages, and includes two busses, which are data write only busses and arranged at different data writing directions independently from each other,
wherein the processing element and the stage memory in one of the data processing stages are connected to each other via a read only bus,
wherein the processing element and the slotted bus in the one of the data processing stages are connected to each other via a write only bus,
wherein a process completion event is input from the processing element to the event controller in the one of the data processing stages, and an external event is input from an external device to the event controller, and
wherein the event controller generates a task start event with respect to the processing element in the one of the data processing stages, according to each of the process completion event and the external event.

2. The data processing device according to claim 1 ,
wherein the at least one processing element includes a plurality of processing elements and an instruction memory,
wherein each of the processing elements includes a local data memory and a task control memory, and
wherein the task control memory in each of the processing elements controls a task, which is executed by each of the processing elements, individually.

3. The data processing device according to claim 2 ,
wherein each of the processing elements includes a first execution unit for processing one piece of data with respect to one instruction and a second execution unit for processing a plurality of pieces of data with respect to one instruction,
wherein the first execution unit is connected to the local data memory via a first data bus,
wherein the second execution unit is connected to the local data memory via the first data bus, and the second execution unit is connected to the slotted bus via a second data bus, and
wherein the second data bus has a bus capacity larger than the first data bus.

4. The data processing device according to claim 1 ,
wherein the plurality of data processing stages are connected to an external connection bus for transferring write data to an external device and transferring the write data from the external device.

5. The data processing device according to claim 4 ,
wherein the external connection bus is connected to the plurality of data processing stages via the slotted bus.

6. The data processing device according to claim 1 ,
wherein the processing element mounted on each of the plurality of data processing stages has a different structure, which corresponds to a process property of each of the plurality of data processing stages.

7. The data processing device according to claim 1 ,
wherein each of the plurality of data processing stages is connected to the slotted bus via an access point,
wherein the access point of one of the data processing stages arranged on one end or the other end of the data processing device includes a loop path for outputting and turning back data, which is input from an adjacent access point, to the adjacent access point,
wherein the access point of another one of the data processing stages arranged between the one end and the other end of the data processing device has a first function for inputting and outputting data, which is transferred in both directions via the slotted bus, to the another one of the data processing stages, or a second function for inputting and outputting data, which is transferred in only one direction via the slotted bus, to the another one of the data processing stages, and
wherein one of the first function and the second function is preliminary selected.

8. The data processing device according to claim 7 ,
wherein at least the access point of the another one of the data processing stages arranged between the one end and the other end of the data processing device includes the loop path.

Assignees

• Denso Corp

Inventors

• Yamamoto Hirofumi
• Funazaki Tomoyoshi

Classifications

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F9/4843

  by program, e.g. task dispatcher, supervisor, operating system · CPC title

• G06F13/372 Primary

  using a time-dependent priority, e.g. individually loaded time counters or time slot · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title