Intelligent refresh of 3D NAND

Patent metadata

Field	Value
Publication number	US-9747158-B1
Application number	US-201715406484-A
Country	US
Kind code	B1
Filing date	Jan 13, 2017
Priority date	Jan 13, 2017
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks of the flash memory for a refresh operation and writing information regarding the identified blocks, to a data structure. The method includes issuing background reads to the identified blocks, according to the data structure, as the refresh operation. The method may be embodied on a computer readable medium. In some embodiments the background reads may be based on a time based refresh responsive to an increase in raw bit error count in the flash memory over time.

First claim

What is claimed is:

1. A tangible, non-transitory, computer-readable media having instructions thereupon which, when executed by a processor, cause the processor to perform a method comprising:
identifying a plurality of blocks of flash memory for a refresh operation;
writing information regarding the identified blocks to a data structure accessible by a hardware engine that sequences background reads of the identified blocks as the refresh operation; and
distributing the background reads to a plurality of channels communicating with the flash memory, wherein the plurality of channels has arbitration of read operations for user data, read operations for metadata, write operations for user data, write operations for metadata, background maintenance operations, erase operations, and the background reads.

2. The computer-readable media of claim 1 , wherein the method further comprises:
receiving a request to read a file; and
determining portions of data belonging to the file, wherein the identifying the plurality of blocks comprises determining blocks of the flash memory that include the portions of data belonging to the file.

3. The computer-readable media of claim 1 , wherein the identifying the plurality of blocks of the flash memory comprises identifying blocks of the flash memory that include filesystem metadata.

4. The computer-readable media of claim 1 , wherein the method further comprises:
communicating a time interval to a hardware engine that cycles the background reads according to the time interval, and wherein the background reads avoids any transfer of data from the identified blocks.

5. The computer-readable media of claim 1 , wherein the method further comprises:
identifying further blocks of the flash memory for the refresh operation; and
updating the data structure with information regarding the further blocks.

6. A storage system, comprising:
a flash memory;
one or more processors, configurable to identify blocks of the flash memory for a refresh operation and the one or more processors configurable to write information regarding the identified blocks;
a hardware engine, configurable to sequence background reads of the identified blocks according to the information as the refresh operation;
an arbiter, configurable to arbitrate read operations for user data or metadata, write operations for user data or metadata, background maintenance operations, erase operations, and the background reads, for a plurality of channels; and
a further memory configurable to hold a data structure, wherein the one or more processors are configurable to write the information regarding the identified blocks to the data structure.

7. The storage system of claim 6 , wherein the one or more processors is configurable to determine which blocks of the flash memory have portions of data that belong to a file, responsive to receiving a request to read the file.

8. The storage system of claim 6 , wherein the one or more processors are configurable to determine which blocks of the flash memory have filesystem metadata.

9. The storage system of claim 6 , wherein the hardware engine is configurable to sequence the background reads in a cycle within a predetermined time interval, and wherein the background reads disregard read data values.

10. The storage system of claim 6 , further comprising:
a plurality of hardware engines, distributed throughout the storage system; and
a plurality of data structures, distributed throughout the storage system, each one of the plurality of data structures associated with one of the hardware engines.

11. The storage system of claim 6 , further comprising:
the one or more processors further configurable to identify further blocks of the flash memory for the refresh operation and configurable to update the data structure regarding the further blocks and wherein the flash memory is three dimensional (3D) flash memory.

Assignees

• Pure Storage Inc

Inventors

• Kannan Hari
• Lee Robert
• Mao Yuhong

Classifications

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G06F11/108

  Parity data distribution in semiconductor storages, e.g. in SSD · CPC title

• H04L1/20

  using signal quality detector · CPC title

• G06F3/0617

  in relation to availability · CPC title