Method for memory storage and access
US-2024126640-A1 · Apr 18, 2024 · US
Memory device with variable code rate
US9201728B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9201728-B2 |
| Application number | US-201314025327-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 12, 2013 |
| Priority date | Sep 12, 2013 |
| Publication date | Dec 1, 2015 |
| Grant date | Dec 1, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload. The processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the parity data responsive to at least a selected one of an accumulated count of access operations upon the selected location or an error rate associated with the selected location.
First claim
Opening claim text (preview).
What is claimed is: 1. An apparatus comprising: a solid-state non-volatile memory; and a processing circuit configured to write data to a selected location of the memory in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload, wherein the processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the p…
Assignees
Inventors
Classifications
- G06F11/1012Primary
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9201728B2 cover?
- Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct o…
- Who is the assignee on this patent?
- Seagate Technology Llc
- What technology area does this patent fall under?
- Primary CPC classification G06F11/1012. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).