Guest-specific microcode

Patent metadata

Field	Value
Publication number	US-9747118-B2
Application number	US-34930709-A
Country	US
Kind code	B2
Filing date	Jan 6, 2009
Priority date	Jan 6, 2009
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

Embodiments of apparatuses, methods, and systems for modifying the behavior of a guest installed to run within a VM are disclosed. In one embodiment, an apparatus includes virtualization logic, first storage, second storage, decode logic, and multiplexing logic. The virtualization logic is to provide a mode in which to operate a virtual machine. The first storage is to store a first plurality of micro-instructions to control the apparatus. The second storage is to store a second plurality of micro-instructions to control the apparatus. The decode logic is to decode a macro-instruction into one of a first plurality and a second plurality of micro-instructions. The multiplexing logic is to cause the macro-instruction to be decoded into the second plurality of micro-instructions instead of the first plurality of micro-instructions only when issued from the virtual machine.

First claim

What is claimed is:

1. A method comprising:
decoding, by decode circuitry of a processor, a first macro-instruction first issued by a guest of a virtual machine managed by a virtual machine monitor, -into a first group of micro-instructions, using a read-only micro-instruction storage, the read-only micro-instruction storage storing native microcode to support a native instruction set architecture of the processor, wherein the virtual machine including its guest and the virtual machine monitor are all running on the processor, the first macro-instruction is first issued by the guest on transfer of control of the processor to the guest from the virtual machine monitor, after the virtual machine monitor storing guest-specific microcode into a writeable micro-instruction storage;
executing, by the processor, the first group of micro-instructions in response to the first issue of the first macro-instruction to execute the first issue of the first macro-instruction in a first way;
determining, by multiplexing circuitry of the processor based on a multiplexer control indicator, without exiting the virtual machine, that the first macro-instruction from a second issuance by the guest is to be decoded using writeable micro-instruction storage instead of the read-only micro-instruction storage, wherein the multiplexer control indicator is set on detecting a condition indicating that a modification to behavior of the guest is desired; the first macro-instruction is second issued by the guest, on transfer of control of the processor from the virtual machine monitor to the guest, after the multiplexer control indicator is set by the virtual machine monitor to indicate that the first macro-instruction is to be decoded using the writeable micro-instruction storage to allow the processor to execute the first macro-instruction as an instruction not in the native instruction set architecture of the processor, wherein the multiplexer control indicator is set by the virtual machine monitor on detecting a condition indicating that a modification to the behavior of the guest is desired;
decoding, by the decode circuitry, without exiting the virtual machine, the first macro-instruction from the second issuance-, into a second group of micro-instructions different from the first group of micro-instructions, using the guest-specific microcode in the writeable micro-instruction storage; and
executing, by the processor, without exiting the virtual machine, the second group of micro-instructions in response to the first macro-instruction from the second issuance to allow the processor to execute the first macro-instruction from the second issuance, in a second way that is different from the first way.

2. A method comprising:
storing, by a virtual machine monitor running on a processor, guest-specific microcode into a writeable micro-instruction storage;
transferring control of the processor from the virtual machine monitor to a guest running on a virtual machine on the processor, the virtual machine being managed by the virtual machine monitor;
wherein the guest, on receipt of control, first issues a first macro-instruction; a
decode circuitry of the processor, on first issue of the first macro-instruction, decodes the first macro-instruction using a read-only micro-instruction storage, into a first group of micro-instructions, the read-only micro-instruction storage storing native microcode to support a native instruction set architecture of the processor; and the processor executes the first group of micro-instructions in response to the first issue of the first macro-instruction to execute the first issue of the first macro-instruction in a first way;

detecting a condition indicating that a modification to behavior of the guest is desired;
setting, by the virtual machine monitor, a multiplexer control indicator to indicate that the first macro-instruction is to be decoded using the writeable micro-instruction storage to allow the processor to execute the first macro-instruction as an instruction not in the native instruction set architecture of the processor; and
transferring control of the processor from the virtual machine monitor to the guest running on the virtual machine on the processor;
wherein the guest, on receipt of control, second issues the first macro-instruction;
multiplexing circuitry of the processor determines based on a multiplexer control indicator, without exiting the virtual machine, that the second issue of the first macro-instruction is to be decoded using writeable micro-instruction storage instead of the read-only micro-instruction storage; the decode circuitry, without exiting the virtual machine, decodes the first macro-instruction using the guest-specific microcode in the writeable micro-instruction storage, into a second group of micro-instructions different from the first group of micro-instructions; and the processor, without exiting the virtual machine, executes the second group of micro-instructions in response to the second issue of the first macro-instruction to allow the processor to execute the second issue of the first macro-instruction in a second way that is different from the first way.

3. A processor comprising:
decode circuitry to decode a first macro-instruction first issued by a guest of a virtual machine managed by a virtual machine monitor, into a first group of micro-instructions, using a read-only micro-instruction storage, the virtual machine including its guest and the virtual machine monitor are running on the processor, the read-only micro-instruction storage storing native microcode to support a native instruction set architecture of the processor, and the first macro-instruction is first issued by the guest on transfer of control of the processor to the guest from the virtual machine monitor, after the virtual machine monitor storing guest-specific microcode into a writeable micro-instruction storage;
an execution unit to execute the first group of micro-instructions in response to the first issue of the first macro-instruction to execute the first issue of the first macro-instruction in a first way; and
multiplexing circuitry to determine based on a multiplexer control indicator, without exiting the virtual machine, that the first macro-instruction from a second issuance by the guest, is to be decoded using writeable micro-instruction storage instead of the read-only micro-instruction storage, wherein the multiplexer control indicator is set on detection of a condition that indicates a modification to behavior of the guest is desired; the first macro-instruction is second issued by the guest, on transfer of control of the processor from the virtual machine monitor to the guest, after the multiplexer control indicator is set by the virtual machine monitor to indicate that the first macro-instruction is to be decoded using the writeable micro-instruction storage to allow the processor to execute the first macro-instruction as an instruction not in the native instruction set architecture of the processor, wherein the multiplexer control indicator is set by the virtual machine monitor on detecting a condition indicating that a modification to the behavior of the guest is desired;
wherein the decode circuitry is to further decode, without exiting the virtual machine, the first macro-instruction from the second issuance, into a second group of micro-instructions different from the first group of micro-instructions, using the guest-specific microcode in the writeable micro-instruction storage; and
wherein the execution unit is to execute, without exiting the virtual machine, the second group of micro-instructions in response to the first macro-instruction from the second issuance to allow the processor to execute the first macro-instruction from the second issuance, in a second way that is different from the first way.

Assignees

• Maliszewski Richard L
• Held James P
• Baumberger Daniel
• Intel Corp

Inventors

• Maliszewski Richard L
• Held James P
• Baumberger Daniel

Classifications

• G06F9/30174

  for non-native instruction set, e.g. Javabyte, legacy code · CPC title

• G06F9/45533 Primary

  Hypervisors; Virtual machine monitors · CPC title

• G06F9/30189

  according to execution mode, e.g. mode flag · CPC title

• G06F9/22

  Microcontrol or microprogram arrangements · CPC title