Semiconductor integrated circuit

Patent metadata

Field	Value
Publication number	US-9742405-B2
Application number	US-201414339509-A
Country	US
Kind code	B2
Filing date	Jul 24, 2014
Priority date	Aug 30, 2013
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

A semiconductor integrated circuit includes: a first wire through which a signal is transmitted; a second wire that is not used for signal transmission; a switch that creates or breaks an electric connection between the first wire and the second wire; and a control circuit that controls the switch according to an potential of the signal, which is transmitted through the first wire, so that part of charge stored in a first wire capacitor of the first wire moves to a second wire capacitor of the second wire and is stored in the second wire capacitor and the charge stored in the second wire capacitor are drawn to the first wire capacitor to charge the first wire capacitor.

First claim

What is claimed is:

1. A semiconductor integrated circuit comprising:
a first wire through which a signal is transmitted;
a first capacitor having a first terminal coupled to the first wire and a second terminal that is grounded;
a second wire that is not used for signal transmission;
a second capacitor having a first terminal coupled to the second wire and a second terminal that is grounded;
a first switch that creates or breaks an electric connection between the first wire and the second wire; and
a control circuit that includes:
a high side switch having a first terminal supplied with a power supply voltage and a second terminal coupled to the first wire, and
a low side switch having a first terminal coupled to the first wire and a second terminal that is grounded, wherein:
the control circuit is configured to turn on the high side switch and to turn off the low side switch and the first switch when the signal is high level,
the control circuit is configured to turn off the high side switch and the low side switch and to turn on the first switch when the signal is changed from the high level to low level, and
the control circuit is configured to turn on the low side switch and to turn off the first switch when the signal is the low level.

2. The semiconductor integrated circuit according to claim 1 , further comprising:
a selector that selects the first wire and the second wire from a plurality of wires, wherein
the selector couples the selected first wire to the second wire through the first switch.

3. The semiconductor integrated circuit according to claim 2 , wherein
the selector couples a plurality of second wires to a single first wire through the first switch.

4. The semiconductor integrated circuit according to claim 1 , further comprising:
a delay circuit that delays the electric connection between the first wire and the second wire from being broken by the first switch according to a time taken until movement of charge is completed between the first capacitor and the second capacitor is completed.

5. The semiconductor integrated circuit according to claim 4 , wherein
the delay circuit enables or disables according to a signal setting to determine whether to reuse charge.

Assignees

• Fujitsu Ltd

Inventors

• Tamura Hirotaka
• Fujisawa Hisanori
• Fujimoto Hiroaki
• Huda Safeen
• Anderson Jason

Classifications

• H03K19/0019 Primary

  by energy recovery or adiabatic operation · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• Y10T307/832

  Cross-Sectional Technologies · mapped topic

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title