Direct current voltage conversion device and clamping circuit
US-9537412-B2 · Jan 3, 2017 · US
US9742279B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9742279-B2 |
| Application number | US-201615003931-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 22, 2016 |
| Priority date | Oct 29, 2015 |
| Publication date | Aug 22, 2017 |
| Grant date | Aug 22, 2017 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
An interleaved buck converter performs buck conversion by controlling operation of each of two switches thereof between an ON state and an OFF state. The switches have the same switching period and the same ON time interval, and a time delay from switching of one of the switches into the ON state to switching of the other one of the switches into the ON state equals the ON time interval of the switches minus a predetermined time interval.
Opening claim text (preview).
What is claimed is: 1. An interleaved buck converter comprising: a first switch having a first terminal that is used to receive an input voltage, a second terminal and a control terminal; a second switch having a first terminal that is coupled to said first terminal of said first switch, a second terminal and a control terminal; a third switch having a first terminal that is coupled to said second terminal of said first switch, and a second terminal that is coupled to a reference node; a fourth switch having a first terminal that is coupled to said second terminal of said second switch, and a second terminal that is coupled to the reference node; a first inductor having a first terminal that is coupled to said second terminal of said first switch, and a second terminal that is used to provide an output voltage; a second inductor coupled between said second terminal of said second switch and said second terminal of said first inductor; a third inductor coupled between said second terminals of said first and second switches; an output capacitor coupled between said second terminal of said first inductor and the reference node; and a controller coupled to said control terminals of said first and second switches, and controlling operation of each of said first and second switches between an ON state and an OFF state such that said first and second switches have the same switching period and the same ON time interval, and such that a time delay from switching of said first switch into the ON state to switching of said second switch into the ON state equals the ON time intervals of said first and second switches minus a predetermined time interval, a value of the time delay being a function of a duty cycle of operation of said first and second switches. 2. The interleaved buck converter of claim 1 , wherein said controller is coupled further to said second terminal of said first inductor for receiving the output voltage therefrom, and controls, based on the output voltage, operation of each of said first and second switches between the ON state and the OFF state so that at least one of the switching period and the ON time interval of said first and second switches is variable. 3. The interleaved buck converter of claim 2 , wherein said controller uses proportional-integral-derivative control techniques to control, based on the output voltage, operation of each of said first and second switches between the ON state and the OFF state. 4. The interleaved buck converter of claim 1 , wherein each of said first and second switches is an N-type metal oxide semiconductor field effect transistor (nMOSFET). 5. The interleaved buck converter of claim 4 , wherein said nMOSFET has a drain terminal, a source terminal and a gate terminal that respectively serve as said first, second and third terminals of a respective one of said first and second switches. 6. The interleaved buck converter of claim 1 , wherein each of said third and fourth switches is a diode. 7. The interleaved buck converter of claim 6 , wherein said diode has a cathode and an anode that respectively serve as said first and second terminals of a respective one of said third and fourth switches. 8. The interleaved buck converter of claim 1 , wherein the controller varies (1) the switching period of said first and second switches responsive to the duty cycle of operation of said first and second switches being greater than a predetermined value, or (2) the ON time interval of said first and second switches responsive to the duty cycle of operation of said first and second switches being less than the predetermined value. 9. An interleaved buck converter comprising: a first switch having a first terminal that is used to receive an input voltage, a second terminal and a control terminal; a second switch having a first terminal that is coupled to said first terminal of said first switch, a second terminal and a control terminal; a third switch having a first terminal that is coupled to said second terminal of said first switch, and a second terminal that is coupled to a reference node; a fourth switch having a first terminal that is coupled to said second terminal of said second switch, and a second terminal that is coupled to the reference node; a first inductor having a first terminal that is coupled to said second terminal of said first switch, and a second terminal that is used to provide an output voltage; a second inductor coupled between said second terminal of said second switch and said second terminal of said first inductor; a third inductor coupled between said second terminals of said first and second switches; an output capacitor coupled between said second terminal of said first inductor and the reference node; and a controller coupled to said control terminals of said first and second switches, and controlling operation of each of said first and second switches between an ON state and an OFF state such that said first and second switches have the same switching period and the same ON time interval, and such that a time delay from switching of said first switch into the ON state to switching of said second switch into the ON state equals the ON time intervals of said first and second switches minus a predetermined time interval, said controller is coupled further to said second terminal of said first inductor for receiving the output voltage therefrom, and controls, based on the output voltage, operation of each of said first and second switches between the ON state and the OFF state so that when the ON time interval divided by the switching period times 100% is greater than a predetermined value, the switching period of said first and second switches is variable; and when the ON time interval divided by the switching period times 100% is less than the predetermined value, the ON time interval of said first and second switches is variable.
Electricity · mapped topic
with a plurality of power processing stages connected in parallel · CPC title
including plural semiconductor devices as final control devices for a single load · CPC title
with automatic control of output voltage or current, e.g. switching regulators · CPC title
switched with a phase shift, i.e. interleaved · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.