Array substrate and manufacturing method thereof, and display apparatus thereof

Patent metadata

Field	Value
Publication number	US-9741753-B2
Application number	US-201615189645-A
Country	US
Kind code	B2
Filing date	Jun 22, 2016
Priority date	Sep 17, 2015
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

An embodiment of the present disclosure provides an array substrate and a manufacturing method thereof and a display apparatus. The array substrate includes a base substrate, wherein, the base substrate is provided with a bonding region; a bonding pad and a first bonding lead connected with the bonding pad and extending to an edge of the base substrate are provided in the bonding region, and one or more metal patterns are arranged above the first bonding lead, the one or more metal patterns crossing over the first bonding lead and being insulated from the first bonding lead.

First claim

The invention claimed is:

1. A manufacturing method of an array substrate, comprising: forming a bonding pad and a first bonding lead, connected with the bonding pad and extending to an edge of a base substrate, in a bonding region of the base substrate, and forming one or more metal patterns above the first bonding lead, the one or more metal patterns crossing over the first bonding lead and being insulated from the first bonding lead.

2. The manufacturing method of the array substrate according to claim 1 , wherein the base substrate is further provided with a display region, the bonding region is located around the display region, and the one or more metal patterns are located on a side of the bonding pad opposite to the display region.

3. The manufacturing method of the array substrate according to claim 1 , further comprising: forming gate lines, a gate insulating layer, data lines and a passivation layer in a display region of the base substrate, wherein,
the bonding region is located around the display region,
the first bonding lead and the gate lines are formed by a same patterning process,
the one or more metal patterns and the data lines are formed by a same patterning process, and
the gate insulating layer extends to a position between the first bonding lead and the one or more metal patterns to insulate the first bonding lead from the one or more metal patterns.

4. The manufacturing method of the array substrate according to claim 3 , wherein, the passivation layer extends to a region of the bonding region without the one or more metal patterns.

5. The manufacturing method of the array substrate according to claim 1 , wherein, the one or more metal patterns are strip-shaped.

6. The manufacturing method of the array substrate according to claim 5 , wherein the metal patterns are parallel with each other.

7. The manufacturing method of the array substrate according to claim 5 , wherein, an extending direction of the one or more metal patterns is vertical to that of the first bonding lead.

8. The manufacturing method of the array substrate according to claim 7 , further, comprising: forming a plurality of second bonding leads parallel with the first bonding lead and located in a same layer as the first bonding lead in the bonding region, wherein, the one or more metal patterns cross over the first bonding lead and the second bonding leads, and the one or more metal patterns are insulated from the second bonding leads.

9. An array substrate, comprising:
a base substrate, provided with a bonding region;
a bonding pad and a first bonding lead, connected with the bonding pad and extending to an edge of the base substrate, provided in the bonding region; and
one or more metal patterns arranged above the first bonding lead, the one or more metal patterns crossing over the first bonding lead and being insulated from the first bonding lead.

10. The array substrate according to claim 9 , wherein the base substrate is further provided with a display region, the bonding region is located around the display region, and the one or more metal patterns are located on a side of the bonding pad opposite to the display region.

11. A display apparatus, comprising the array substrate according to claim 9 .

12. The array substrate according to claim 9 , wherein the base substrate is further provided with a display region, the bonding region is located around the display region, the display region includes gate lines, a gate insulating layer, data lines and a passivation layer sequentially arranged on the base substrate, the first bonding lead and the gate lines are made of a same material and arranged in a same layer, the one or more metal patterns and the data lines are made of a same material and arranged in a same layer, and the gate insulating layer extends to a position between the first bonding lead and the one or more metal patterns to insulate the first bonding lead from the one or more metal patterns.

13. The array substrate according to claim 12 , wherein the passivation layer further extends to a region of the bonding region without the one or more metal patterns.

14. The array substrate according to claim 9 , wherein the one or more metal patterns are strip-shaped.

15. The array substrate according to claim 14 , wherein, the base substrate is further provided with a display region, the bonding region is located around the display region, and the one or more metal patterns are located on a side of the bonding pad opposite to the display region.

16. The array substrate according to claim 14 , wherein the metal patterns are parallel with each other.

17. The array substrate according to claim 14 , wherein an extending direction of the one or more metal patterns is vertical to that of the first bonding lead.

18. The array substrate according to claim 17 , wherein the metal patterns are parallel with each other.

19. The array substrate according to claim 17 , wherein the bonding region is further provided with a plurality of second bonding leads parallel with the first bonding lead and located in a same layer as the first bonding lead, the one or more metal patterns cross over the first bonding lead and the second bonding leads, and the one or more metal patterns are insulated from the second bonding leads.

20. The array substrate according to claim 19 , wherein the metal patterns are parallel with each other.

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Gao Jilei
• Jiang Xuebing
• Zhao Jian

Classifications

• H10W72/90

  Bond pads, in general · CPC title

• H01L27/14603 Primary

  Electricity · mapped topic

• H01L27/14812

  Electricity · mapped topic

• H01L27/3248

  Electricity · mapped topic

• H01L24/08

  Electricity · mapped topic