Electronic chip comprising multiple layers for protecting a rear face

Patent metadata

Field	Value
Publication number	US-9741670-B2
Application number	US-201615131378-A
Country	US
Kind code	B2
Filing date	Apr 18, 2016
Priority date	Apr 20, 2015
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

An electronic chip and a method of making thereof is provided, where the electronic chip includes at least: an electronic circuit arranged at a front face of a substrate; a first protective layer arranged on a rear face of the substrate; a resistive element arranged on the first protective layer and facing at least one part of the electronic circuit, mechanically supported by the first protective layer and connected electrically and/or in an inductive manner to the electronic circuit; a second protective layer covering at least the resistive element; and in which the first protective layer comprises at least one dielectric material having a resistance to chemical etching by at least one chemical etching agent less than or equal to that of a dielectric material of the second protective layer.

First claim

The invention claimed is:

1. An electronic chip comprising at least:
an electronic circuit arranged at a front face of a substrate;
a first protective layer arranged on a rear face of the substrate;
a resistive element arranged on the first protective layer and facing at least one part of the electronic circuit, mechanically supported by the first protective layer and connected electrically and/or in an inductive manner to the electronic circuit;
a second protective layer disposed beneath the rear face of the substrate without being disposed over the front face of the substrate and covering at least the resistive element;
and in which the first protective layer comprises at least one dielectric material having a resistance to chemical etching by at least one chemical etching agent less than or equal to that of a dielectric material of the second protective layer.

2. The electronic chip according to claim 1 , in which at least the dielectric material of the second protective layer comprises at least one of the following characteristics: resistant to mechanical polishing, opaque towards infrared radiation, and resistant to an attack by focused ion beam.

3. The electronic chip according to claim 2 , in which at least the dielectric material of the second protective layer has a Young's modulus greater than or equal to around 1 GPa.

4. The electronic chip according to claim 1 , in which the dielectric material of the first protective layer and/or the dielectric material of the second protective layer is a non-mineral material and/or a polymer and/or comprises epoxy and/or comprises silicone.

5. The electronic chip according to claim 1 , in which the first protective layer and/or the second protective layer further comprises particles of a first material different to the dielectric material of the first protective layer and/or the dielectric material of the second protective layer, and which are spread out in the whole of the dielectric material of the first protective layer and/or the dielectric material of the second protective layer.

6. The electronic chip according to claim 5 , in which the first material of the particles comprises at least one of silica and alumina.

7. The electronic chip according to claim 5 , in which the first material of the particles is covered with a second reflective material towards light and/or electronic and/or ionic radiation.

8. The electronic chip according to claim 1 , in which the resistive element comprises at least one conducting track having at least one serpentine pattern and/or several alternating, entangled, wound up or intertwined patterns.

9. The electronic chip according to claim 8 , in which the conducting track has a width comprised between around 5 μm and 50 μm, and/or in which the portions of the conducting track which are next to and parallel to each other are spaced apart by a distance comprised between around 5 μm and 50 μm.

10. The electronic chip according to claim 1 , further comprising an electrically conducting layer arranged between the rear face of the substrate and the first protective layer.

11. The electronic chip according to claim 1 , further comprising at least two first conducting vias made through the substrate and electrically connecting the resistive element to the electronic circuit.

12. The electronic chip according to claim 1 , further comprising an inductive element arranged at the front face of the substrate and electrically connected to the electronic circuit, and in which the resistive element forms part of a RLC (resistor, inductor, and capacitor) circuit capable of being coupled in an inductive manner with said inductive element such that a modification of a value of an inductance of the inductive element induces a modification of an electrical property of the RLC circuit.

13. The electronic chip according to claim 12 , in which the inductive element is integrated in the electronic circuit.

14. The electronic chip according to claim 12 , in which the resistive element forms a coil of which the ends are electrically connected to each other.

15. The electronic chip according to claim 1 , further comprising at least one second via and/or a trench made through the rear face of the substrate and only a part of the thickness of the substrate, and arranged at least facing the electronic circuit such that a bottom wall of the second via and/or of the trench is spaced apart from the electronic circuit by a non-zero distance.

16. A method for producing an electronic chip comprising at least the steps of:
producing an electronic circuit at a front face of a substrate;
producing a first protective layer on a rear face of the substrate;
producing at least one resistive element on the first protective layer and facing at least one part of the electronic circuit, the resistive element being mechanically supported by the first protective layer and connected electrically and/or in an inductive manner to the electronic circuit;
producing a second protective layer disposed beneath the rear face of the substrate without being disposed over the front face of the substrate and covering at least the resistive element;
and in which the first protective layer comprises at least one dielectric material having a resistance to chemical etching by at least one chemical etching agent less than or equal to that of a dielectric material of the second protective layer.

Assignees

• Commissariat Energie Atomique
• Commissariat L Energie Atomique Et Aux Energies Alternatives

Inventors

• Charbonnier Jean
• Borel Stephan

Classifications

• H10W42/405

  using active circuits · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W42/40 Primary

  protecting against tampering, e.g. unauthorised inspection or reverse engineering · CPC title

• H10W42/00 Primary

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H01L23/576

  Electricity · mapped topic