Dense interconnect with solder cap (DISC) formation with laser ablation and resulting semiconductor structures and packages

Patent metadata

Field	Value
Publication number	US-9741645-B2
Application number	US-201113995629-A
Country	US
Kind code	B2
Filing date	Dec 21, 2011
Priority date	Dec 21, 2011
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

Dense interconnect with solder cap (DISC) formation with laser ablation and resulting semiconductor structures and packages are described. For example, a method of fabricating a semiconductor structure includes forming an insulative material stack above a plurality of solder bump landing pads. The solder bump landing pads are above an active side of a semiconductor die. A plurality of trenches is formed in the insulative material stack by laser ablation to expose a corresponding portion of each of the plurality of solder bump landing pads. A solder bump is formed in each of the plurality of trenches. A portion of the insulative material stack is then removed.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a substrate having a land side, wherein the substrate comprises a fan-out layer, and wherein the substrate is a bumpless build-up layer (BBUL) substrate; and
a semiconductor die fully embedded and surrounded by an encapsulating film of the BBUL substrate, the semiconductor die comprising:
an active side proximate to the land side of the substrate;
a photo-insensitive solder mask disposed on the active side of the semiconductor die, between the semiconductor die and the substrate, the photo-insensitive solder mask comprising a plurality of trenches exposing a corresponding portion of each of a plurality of solder bump landing pads, wherein the photo-insensitive solder mask is distinct from the encapsulating film and does not extend beyond the active side of the semiconductor die; and
a solder bump disposed in each of the plurality of trenches.

2. The semiconductor package of claim 1 , wherein the substrate is a coreless substrate.

3. The semiconductor package of claim 1 , wherein the semiconductor die is housed in a core of the substrate.

4. The semiconductor package of claim 1 , wherein the photo-insensitive solder mask comprises a material selected from the group consisting of an inorganic dielectric material and an organic dielectric material.

5. The semiconductor package of claim 1 , wherein the plurality of solder bump landing pads is formed above a low-k dielectric layer of the active side of the semiconductor die.

6. The semiconductor package of claim 1 , wherein the plurality of trenches has a pitch of, or less than, approximately 90 microns.

7. A semiconductor package, comprising:
a substrate having a land side, wherein the substrate is a bumpless build-up layer (BBUL) substrate; and
a semiconductor die fully embedded and surrounded by an encapsulating film of the BBUL substrate, the semiconductor die comprising:
an active side proximate to the land side of the substrate;
a photo-insensitive solder mask disposed on the active side of the semiconductor die, between the semiconductor die and the substrate, the photo-insensitive solder mask comprising a plurality of trenches exposing a corresponding portion of each of a plurality of solder bump landing pads, wherein the photo-insensitive solder mask comprises a material selected from the group consisting of an inorganic dielectric material and an organic dielectric material, and wherein the photo-insensitive solder mask is distinct from the encapsulating film and does not extend beyond the active side of the semiconductor die; and
a solder bump disposed in each of the plurality of trenches.

8. The semiconductor package of claim 7 , wherein the substrate is a coreless substrate.

9. The semiconductor package of claim 7 , wherein the semiconductor die is housed in a core of the substrate.

10. The semiconductor package of claim 7 , wherein the plurality of solder bump landing pads is formed above a low-k dielectric layer of the active side of the semiconductor die.

11. The semiconductor package of claim 7 , wherein the plurality of trenches has a pitch of, or less than, approximately 90 microns.

12. A semiconductor package, comprising:
a substrate having a land side, wherein the substrate is a bumpless build-up layer (BBUL) substrate; and
a semiconductor die fully embedded and surrounded by an encapsulating film of the BBUL substrate, the semiconductor die comprising:
an active side proximate to the land side of the substrate;
a photo-insensitive solder mask disposed on the active side of the semiconductor die, between the semiconductor die and the substrate, the photo-insensitive solder mask comprising a plurality of trenches exposing a corresponding portion of each of a plurality of solder bump landing pads, wherein the plurality of solder bump landing pads is formed above a low-k dielectric layer of the active side of the semiconductor die, and wherein the photo-insensitive solder mask is distinct from the encapsulating film and does not extend beyond the active side of the semiconductor die; and
a solder bump disposed in each of the plurality of trenches.

13. The semiconductor package of claim 12 , wherein the substrate is a coreless substrate.

14. The semiconductor package of claim 12 , wherein the semiconductor die is housed in a core of the substrate.

15. The semiconductor package of claim 12 , wherein the plurality of trenches has a pitch of, or less than, approximately 90 microns.

16. A semiconductor package, comprising:
a substrate having a land side, wherein the substrate is a bumpless build-up layer (BBUL) substrate; and
a semiconductor die fully embedded and surrounded by an encapsulating film of the BBUL substrate, the semiconductor die comprising:
an active side proximate to the land side of the substrate;
a photo-insensitive solder mask disposed on the active side of the semiconductor die, between the semiconductor die and the substrate, the photo-insensitive solder mask comprising a plurality of trenches exposing a corresponding portion of each of a plurality of solder bump landing pads, wherein the photo-insensitive solder mask is distinct from the encapsulating film and does not extend beyond the active side of the semiconductor die; and
a solder bump disposed in each of the plurality of trenches, wherein the plurality of trenches has a pitch of, or less than, approximately 90 microns.

17. The semiconductor package of claim 16 , wherein the substrate is a coreless substrate.

18. The semiconductor package of claim 16 , wherein the semiconductor die is housed in a core of the substrate.

Assignees

• Hu Chuan
• Intel Corp

Inventors

• Hu Chuan

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/01257

  by reflowing · CPC title

• H10W72/01255

  by using masks · CPC title

• H10W72/01225

  in solid form, e.g. by using a powder or by stud bumping · CPC title