Methods of fabricating semiconductor devices including supporting patterns in gap regions between conductive patterns

Patent metadata

Field	Value
Publication number	US-9741608-B2
Application number	US-201615093408-A
Country	US
Kind code	B2
Filing date	Apr 7, 2016
Priority date	Sep 5, 2012
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

An integrated circuit device includes spaced apart conductive patterns on a substrate surface, and a supporting pattern on the substrate surface between adjacent ones of the conductive patterns and separated therefrom by respective gap regions. The adjacent ones of the conductive patterns extend away from the substrate surface beyond a surface of the supporting pattern therebetween. A capping layer is provided on respective surfaces of the conductive patterns and the surface of the supporting pattern. Related fabrication methods are also discussed.

First claim

What is claimed is:

1. A method of fabricating an integrated circuit device, the method comprising:
forming spaced apart conductive patterns on a substrate surface;
forming respective supporting patterns on the substrate surface between adjacent ones of the conductive patterns and separated therefrom by respective gap regions by performing a plasma treatment process on respective insulating layers between the adjacent ones of the conductive patterns, wherein the adjacent ones of the conductive patterns extend away from the substrate surface beyond a top surface of the respective supporting pattern therebetween; and
forming a capping layer on respective surfaces of the conductive patterns and on the top surface of the respective supporting patterns.

2. The method of claim 1 , wherein the plasma treatment process increases an etch selectivity of peripheral portions of the respective insulating layers relative to portions thereof that define the respective supporting patterns, and wherein forming the respective supporting patterns further comprises:
selectively etching the peripheral portions of the respective insulating layers between the adjacent ones of the conductive patterns after performing the plasma treatment process.

3. The method of claim 2 , wherein the respective insulating layers comprise a carbon-containing material, and wherein the plasma treatment process removes carbon from the peripheral portions of the respective insulating layers.

4. The method of claim 3 , wherein performing the plasma treatment process comprises supplying a gas comprising H 2 , NH 3 , N 2 H 2 , N 2 O, O 2 , CO 2 , or CO, with a power of 300-800 W at a temperature of 200° C. to 400° C. and a pressure of 3 Torr to 8 Torr.

5. The method of claim 3 , further comprising
forming a sacrificial layer between the adjacent ones of the conductive patterns after forming the respective supporting patterns;
wherein forming a capping layer comprises forming the capping layer on the respective surfaces of the conductive patterns, on the top surface of the respective supporting pattern therebetween, and on the sacrificial layer, and further comprising:
removing the sacrificial layer after forming the capping layer thereon to define the respective gap regions.

6. The method of claim 5 , wherein the sacrificial layer comprises a hydrocarbon-containing material, wherein the respective supporting patterns comprise the carbon-containing material having an ashing selectivity to the hydrocarbon-containing material, and wherein removing the sacrificial layer comprises:
performing an ashing process that decomposes the sacrificial layer into a gas,
wherein the capping layer is configured to permit the gas to be outgassed therethrough.

7. A method of fabricating an integrated circuit device, the method comprising:
forming spaced apart conductive patterns on a substrate surface;
forming respective supporting patterns on the substrate surface between adjacent ones of the conductive patterns and separated therefrom by respective gap regions, by:
performing a plasma treatment process on respective insulating layers between the adjacent ones of the conductive patterns, wherein the plasma treatment process removes carbon from peripheral portions of the respective insulating layers; and
selectively etching the peripheral portions of the respective insulating layers between the adjacent ones of the conductive patterns to define the respective supporting patterns and the respective gap regions separating the respective supporting patterns from the adjacent ones of the conductive patterns,

wherein the adjacent ones of the conductive patterns extend away from the substrate surface beyond a top surface of the respective supporting pattern therebetween; and
forming a capping layer on respective surfaces of the conductive patterns and on the top surface of the respective supporting patterns.

8. The method of claim 7 , wherein, responsive to selectively etching, dimensions of the respective supporting patterns are reduced as spacing between the adjacent ones of the conductive patterns is decreased.

9. A method of fabricating a semiconductor device, comprising:
forming an insulating layer on a substrate;
patterning the insulating layer to form a plurality of recessed regions;
forming conductive patterns to fill the recessed regions;
performing a plasma treatment with respect to the insulating layer;
removing at least a portion of the insulating layer to expose sidewalls of the conductive patterns; and
forming a sacrificial layer to fill a space between the conductive patterns;
forming a capping layer on the conductive patterns and the sacrificial layer; and
removing the sacrificial layer to form an air-gap region between the conductive patterns.

10. The method of claim 9 , wherein the removing at least a portion of the insulating layer comprises forming a supporting pattern, wherein the supporting pattern is in contact with the capping layer after the removal of the sacrificial layer.

11. The method of claim 9 , wherein the removing at least a portion of the insulating layer comprises forming a remaining pattern spaced apart from the capping layer, wherein the remaining pattern is spaced apart from the capping layer after the removal of the sacrificial layer.

12. The method of claim 9 , wherein the recessed regions are formed using an anisotropic etching process.

13. The method of claim 9 , wherein the insulating layer is formed of a carbon-containing material, and wherein the etching process and the plasma treatment are performed to remove carbons from at least a portion of the insulating layer.

14. The method of claim 9 , wherein performing the plasma treatment with respect to the insulating layer comprises supplying at least one gas of H 2 , NH 3 , N 2 H 2 , N 2 O, O 2 , CO 2 , or CO, with a plasma power of 300-800 W at a temperature of 200-400° C. and a pressure of 3-8 Torr.

15. The method of claim 9 , wherein the sacrificial layer is formed of a hydrocarbon layer.

16. The method of claim 9 , wherein the capping layer is formed using at least one deposition process of ALD, PE-CVD, AP-CVD, or FCVD.

17. The method of claim 9 , wherein the removing the sacrificial layer comprises performing an ashing process that decomposes the sacrificial layer into gas that is outgassed through the capping layer.

18. The method of claim 17 , wherein the ashing process comprises supplying at least one gas of NH 3 , H 2 , N 2 O, O 2 , CO 2 , or CO at a temperature of 20-400° C.

19. The method of claim 9 , further comprising forming a first protection layer to cover top surfaces of the conductive patterns, before the removing at least a portion of the insulating layer.

20. The method of claim 19 , further comprising forming a second protection layer to cover the conductive patterns, after the removing at least a portion of the insulating layer and before the forming the sacrificial layer.

Assignees

• Han Kyu-Hee
• Ahn Sanghoon
• Samsung Electronics Co Ltd

Inventors

• Han Kyu-Hee
• Ahn Sanghoon

Classifications

• H10P95/08

  Planarisation of organic insulating materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/037

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title